Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-07-24
2000-09-12
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438488, 438597, 438654, 438652, H01L 213205
Patent
active
061177555
ABSTRACT:
A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped polysilicon layer is deposited on a semiconductor substrate in the integrated circuits, then immediately after the deposition of an undoped polysilicon, the process temperature is reduced and the treatment of purging is followed with, finally, a metal silicide is formed on the undoped polysilcion.
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Chen Chien-Hung
Chen Kuang-Chao
Chung Yi-Fu
Kun-Yu Sung
Duong Khanh
Jr. Carl Whitehead
Mosel Vitelic Inc.
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