Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-07-24
2007-07-24
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S692000, C438S690000, C438S689000, C257SE21206, C257SE21243
Reexamination Certificate
active
11226979
ABSTRACT:
A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
REFERENCES:
patent: 5923993 (1999-07-01), Sahota
patent: 6380078 (2002-04-01), Liu et al.
patent: 6391792 (2002-05-01), Jang et al.
patent: 6521523 (2003-02-01), Lee et al.
patent: 2003/0228734 (2003-12-01), Natsume et al.
patent: 2006/0043590 (2006-03-01), Chen et al.
Chen Pi-Tsung
Chen Ying-Tsung
Lu Yung-Cheng
Wu Zhen-Cheng
Chaudhari Chandra
Kirkpatrick & Lockhart Preston Gates Ellis
Taiwan Semiconductor Manufacturing Co. Ltd.
Yevsikov Victor V.
LandOfFree
Method for planarizing semiconductor structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for planarizing semiconductor structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing semiconductor structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3818796