Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-12-13
2000-08-15
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438256, 438396, 438399, 438643, 438688, H01L 218242
Patent
active
061035696
ABSTRACT:
A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.
REFERENCES:
patent: 5552344 (1996-09-01), Jang et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5726099 (1998-03-01), Jaso
patent: 5804084 (1998-09-01), Nasby et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5858813 (1999-01-01), Scherber et al.
patent: 5910022 (1999-06-01), Weling
patent: 5916855 (1999-06-01), Avanzino et al.
patent: 5960320 (1999-09-01), Park
patent: 6023102 (2000-02-01), Nguyen et al.
patent: 6037213 (2000-03-01), Shih et al.
Chan Lap
Chen Feng
Teo Kok Hin
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Smith Matthew
Stoffel William J.
LandOfFree
Method for planarizing local interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for planarizing local interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing local interconnects will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2005909