Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-07
2003-02-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000, C438S692000, C438S693000
Reexamination Certificate
active
06514821
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91107423, filed Apr. 12, 2002.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a planarizing method. More particularly, the present invention relates to a method for planarizing a dielectric layer of a flash memory.
2. Description of Related Art
Typically, chemical-mechanical polishing (CMP) process is one of the global planarizing processes in the manufacturing process of the ultra large semiconductor integrated circuit. The CMP process based on the mechanical polishing theory and is performed with the aidance of proper chemical reagent to polish the uneven profile.
In the conventional CMP process, the chemical reagent is also called slurry. The slurry is a mixture comprises colloidal-type silica, dispersed-type alumina and basic KOH or NH
4
OH. Basically, such the polishing particles with relatively high hardness mentioned above are used to perform the polishing process on the wafer surface.
FIGS. 1A through 1E
are schematic, cross-section views of a portion of a conventional method for planarizing a dielectric layer of a flash memory.
As shown in
FIG. 1A
, a substrate
100
having several polysilicon gate structures
102
formed thereon is provided. Moreover, every polysilicon gate structure
102
possesses a nitride layer
104
formed on the top of the polysilicon gate structure
102
as a protection.
As shown in
FIG. 1B
, a high density plasma oxide (HDP oxide) layer
106
is formed over the substrate
100
to fill the space between the polysilicon gate structures
102
.
As shown in
FIG. 1C
, an alignment key oxide dipping (AOD) process is performed. It should be noticed that based on the well known photolithography theory, the AOD process is used to remove portions of the dielectric layer formed on the relatively large gate structure. A wet etching process is performed to remove a portions of the HDP oxide layer
106
to expose corners
108
of the polysilicon gate structures
102
. Therefore, the HDP oxide layer
106
is separated into a filling portion
106
a
in the space between the polysilicon gate structure
102
and a covering portion
106
b
on the top of the polysilicon gate structures
102
. A nitride layer
110
is formed over the substrate
100
.
As shown in
FIG. 1D
, a CMP process is performed to planarize the nitride layer
110
and the covering portion
106
b
. An oxide dipping is performed to remove the metal ions formed during performing the CMP process with KOH-containing slurry in order to improve the reliability of the devices. After the oxide dipping process is performed, the thickness of the covering portion
106
b
is about 100 angstroms.
As shown in
FIG. 1E
, the remaining covering portion
106
b
, the nitride layers
110
and
104
.
Because the AOD process is performed before the planarizing process is performed and the portion of the dielectric layer is removed by oxide dipping process to expose the corners of the polysilicon gate structures before the CMP process is performed, it takes a lot of time to finish the whole process procedure and the procedure is complex.
SUMMARY OF THE INVENTION
The invention provides a method of planarizing a dielectric layer of a flash memory. In the present invention, a high selectivity slurry (HSS) is used to planarize a dielectric layer of a flash memory. The high selectivity slurry comprises a Ceria-polishing-particle-containing slurry having CeO
2
and a planarity selective additive having polycarboxylate. The concentration of CeO
2
in the Ceria-polishing-particle-containing slurry is 5 wt % within a tolerance around 25% and the concentration of polycarboxylate in the planarity selective additive is 1-10 wt %.
In the present invention, the HSS possesses relatively high polishing speed for polishing the surface with protuberance portions and relatively low polishing speed for polishing the surface with recess portions so that the process procedure can be simplify by omitting the conventional complex steps such as oxide dipping process, AOD process and silicon nitride deposition. Therefore, the cost can be greatly decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5607718 (1997-03-01), Sasaki et al.
patent: 2002/0100743 (2002-08-01), Bonner et al.
Chen Jack
J. C. Patents
Macronix International Co. Ltd.
Nguyen Tuan H.
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