Method for planarizing a semiconductor substrate

Details Method for planarizing a semiconductor substrate Method for planarizing a semiconductor substrate

1998-05-18

2001-04-10

Bowers, Chares (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S631000, C438S697000, C438S435000, C438S704000

Reexamination Certificate

active

06214735

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method for planarizing a semiconductor substrate, and more particularly to a method for planarizing an interlayer insulating film on a semiconductor substrate using a difference in etch selectivity of insulators.
BACKGROUND OF THE INVENTION
With the gradual increase in integration of semiconductor devices, much effort has been dedicated to planarization processes to planarize an insulating layer, such as an interlayer insulating layer formed on a semiconductor substrate. Recently, STI process known as (Shallow Trench Isolation) has been widely used to electrically isolate device elements on a semiconductor substrate on the behalf of LOCOS process, and increase in step between the device elements requires a variety of planarization techniques.
There have been several processes used to planarize insulating layers, for example, BPSG (Boron Phosphorus Silicate Glass) reflow, SOG (Spin On Glass) or photoresist etch back, and CMP (Chemical Mechanical Polishing). Particularly, CMP can be used to planarize a wider area in comparison with the other processes, and can be performed at a low temperature. Because of these advantages, CMP has come into wide use in substrate planarization. A typical CMP process is disclosed in, for example, U.S. Pat. No. 5,064,683, issued Feb. 27, 1996.
However, substrate planarization using CMP leads to three main problems: first, in a substrate structure having dish-shape, a dishing phenomenon is generated. Second, the substrate is contaminated by a polishing slurry. Third, the substrate and the CMP planarizing apparatus are contaminated by particles generated during the CMP process.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problems encountered in CMP, and it is an object of the invention to provide a method for planarizing a semiconductor substrate using a difference in etch selectivity of insulators.
According to one aspect of the present invention, there is provided a method for planarizing a semiconductor substrate having an uneven topography including an elevated region and a recessed region adjacent to each other. After sequentially forming first and second insulating layers on the semiconductor substrate, a sputter-etching process is performed to remove the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges. Next, a third insulating layer is formed on the first and second insulating layers and then a wetetching process is performed to remove the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching process, since the second insulating layer has a relatively high etch selectivity relative to the first or third insulating layer, the second insulating layer is etched faster than the third insulating layer. The semiconductor substrate may have an even surface.
According to another aspect of the present invention, there is provided a method for planarizing a semiconductor substrate having an uneven topography including an elevated region and an adjacent recessed region. First, second and third insulating layers are sequentially formed on the elevated and recessed regions by either HDP CVD or ECR CVD. The second and third insulating layers are wet-etched to expose an upper surface of the first insulating layer. The second insulating layer is deposited and at the same time etched during formation thereof to etch upper edges of the elevated region faster than the other portions, and thereby the third insulating layer is formed on the second insulating layer including the first insulating layer exposed at the upper edges of the elevated region.


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