Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-25
2003-12-09
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S634000, C438S643000, C438S653000, C438S671000, C438S687000
Reexamination Certificate
active
06660627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for planarization of a semiconductor wafer, and more particularly, to a method for planarization of a semiconductor wafer with a high selectivity utilized in a semiconductor process.
2. Description of the Prior Art
When fabricating modern semiconductor integrated circuits (ICs) in the deep sub-micro field, to prevent subsequent manufacturing processes from being adversely affected, the planarization of each deposition layer of an integrated circuit has to be considered. In fact, most high-density IC fabrication techniques make use of some method to form a planarized wafer surface at critical points in the manufacturing process. One method for achieving semiconductor wafer planarization or topography removal is the chemical mechanical polishing (CMP) process. The CMP process has become an indispensable technique for removing materials on a semiconductor wafer in the back end of the line (BEOL) interconnect process. Especially, since the etching technique for copper has not yet matured, for forming copper wires in an integrated circuit, the CMP process seems to be the only one planarization techniques utilized in the copper interconnect process.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of a copper-damascene structure
10
according to a prior art. The prior art copper-damascene structure
10
includes a first dielectric layer
12
, a first conductive layer
14
, a cap layer
16
, a second dielectric layer
18
, a hard mask
20
, a barrier layer
22
, a second conductive layer
24
, and a via plug
26
. The first conductive layer
14
is composed of metal, and the cap layer
16
is typically composed of silicon nitride (SiN). Furthermore, the second dielectric layer
18
is composed of low dielectric constant material, and the hard mask
20
is made from fluorinated silicate glass (FSG) having a low dielectric constant or typical photoresist material, such as SiO
2
, SiN, SiON, SiC, SiCO, or SiOCN. Additionally, the barrier layer
22
is composed of Ta, TaN, or other conventional barrier material, and both of the second conductive layer
24
and the via plug
26
are made from copper. Thereafter, the copper-damascene structure
10
has a chemical mechanical polishing (CMP) process performed on it to remove the second conductive layer
24
and the portion of barrier layer
22
disposed on the surface of hard mask
20
so as to complete the fabrication of a copper interconnect.
For ensuring the portion of barrier layer
22
disposed on the surface of hard mask
20
can be removed completely, when the CMP process is performed on the barrier layer
22
, the copper-damascene structure
10
has to be over polished appropriately. However, since slurry used currently has similar chemical characteristics with respect to the barrier layer
22
and the hard mask
20
, a removal rate of the barrier layer
22
is close to a removal rate of the hard mask
20
during the CMP process. Therefore, a polishing selectivity for the removal rate of the barrier layer
22
is very small with respect to the hard mask
20
during the CMP process. The so-called polishing selectivity is defined by a ratio of the removal rate of the barrier layer
22
to the removal rate of the hard mask
20
. Typically, the polishing selectivity is smaller than 5. Hence, when the barrier layer
22
of the prior art copper-damascene structure
10
is polished by the CMP process, the hard mask
20
is inevitably polished by the CMP process as well, leading to a thickness of a damaged portion of the hard mask
20
being 300 to 1000 Å. Additionally, the uniformity of the polished surface of the copper-damascene structure
10
may exceed 10% and thus adversely affect the electrical performance of the copper-damascene structure
10
. Moreover, the roughness of the polished surface of the copper-damascene structure
10
causes difficulty in the fabrication of high-level layers when manufacturing a multi-level metal interconnect structure.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the claimed invention to provide a method for planarization of a semiconductor wafer with a high selectivity to solve the above-mentioned problem.
According to the claimed invention, a method for planarization of a semiconductor wafer is disclosed. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method comprises performing a first chemical mechanical polishing (CMP) process on the barrier layer to expose the stop layer, and removing the stop layer. A polishing selectivity for a removal rate of the barrier layer is greater than 50 with respect to the stop layer during the first CMP process. According to the claimed invention, the polishing selectivity for the removal rate of the barrier layer is greater than 100 with respect to the stop layer via selecting appropriate material of the stop layer during the first CMP process.
It is an advantage of the claimed invention that the stop layer is placed in between the hard mask and the barrier layer and the removal rate of the stop layer is substantially different from the removal rate of the barrier layer due to the material of the stop layer. Thus, the prior art problem of loss of the hard mask due to the low polishing selectivity is effectively eliminated. Meanwhile, the surface of semiconductor wafer can be highly planarized through the high selectivity provided by the claimed invention. Furthermore, the process margin can be substantially increased and thus the quality of the semiconductor wafer can be effectively controlled.
REFERENCES:
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6440840 (2002-08-01), Chen
Chen Hsueh-Chung
Hsu Chia-Lin
Hsu Shih-Hsun
Hu Shao-Chung
Coleman W. David
Hsu Winston
Lee Hsien Ming
United Microelectronics Corp.
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