Method for planarization of submicron vias and the manufacture o

Details Method for planarization of submicron vias and the manufacture o Method for planarization of submicron vias and the manufacture o

1993-04-13

1994-11-01

McFarlane, Anthony

Chemistry: electrical and wave energy

Processes and products

Coating, forming or etching by sputtering

20429802, 437203, C23C 1400

Patent

active

053605241

ABSTRACT:
Submicron vias are filled by sputter deposition of a conductor such as aluminum onto a substrate such as silicon or silicon oxides. The deposited aluminum film is deposited at a first lower temperature and then the temperature is increased. The differential coefficient of thermal expansion of the substrate relative to the metal conductor forces the conductor to expand into the via. Maintaining an effective thickness and controlling the temperature increase from the first temperature to the second temperature, effectively and reliably fills submicron vias having aspect ratios up to 4. The present invention is particularly useful with filling vias having re-entrant angles of up to 20.degree..

REFERENCES:
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4661228 (1987-04-01), Mintz
patent: 4816126 (1989-03-01), Kamoshida et al.
patent: 4865712 (1989-09-01), Mintz
patent: 4970176 (1990-11-01), Tracy et al.
patent: 4994162 (1991-02-01), Armstrong et al.
patent: 5071791 (1991-12-01), Inoue et al.
patent: 5108570 (1992-04-01), Wang
Taguchi et al: Quarter Micron Hole Filling With SiN Sidewalls by Aluminum High Temperature Sputtering, Jun. 9-10, 1992 VMIC Conference, pp. 219-225.

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