Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-13
2009-11-10
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07617476
ABSTRACT:
A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of: (a) determining a minimum critical dimension and pitch associated with a process to be utilized to image the multiple patterns; (b) generating an anchoring feature; (c) disposing the anchoring feature adjacent a first feature of the target pattern; (d) growing the anchoring feature a predetermined amount so as to define a first area; (e) assigning any feature within the first area to a first pattern; (f) disposing the anchoring feature adjacent a second feature of the target pattern; (g) growing the anchoring feature the predetermined amount so as to define a second area; and (h) assigning any feature within the second area to a second pattern. Steps (c)-(h) are then repeated until the densely spaced features within the target pattern have been assigned to either the first or second pattern.
REFERENCES:
patent: 7378202 (2008-05-01), Granik et al.
patent: 7488933 (2009-02-01), Ye et al.
Broeke Douglas Van Den
Chen Jang Fung
Corcoran Noel
Hsu Duan-Fu Stephen
ASML Masktools B.V.
Chiang Jack
Pillsbury Winthrop Shaw & Pittman LLP
Tat Binh C
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