Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-10
2005-05-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06892365
ABSTRACT:
A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.
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Culp James A.
Lavin Mark A.
Sayah Robert T.
DeLio & Peterson LLC
International Business Machines - Corporation
Levin Naum
Peterson Peter W.
Schnurmann H. Daniel
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