Method for performing built-in and at-speed test in...

Details Method for performing built-in and at-speed test in... Method for performing built-in and at-speed test in...

2007-06-12

2007-06-12

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000

Reexamination Certificate

active

11160974

ABSTRACT:
A method for performing a built-in and at-speed test in a system-on-chip includes receiving a statistic timing analysis report of the system-on-chip, determining a plurality of critical paths for an at-speed test in the system-on-chip according to the statistic timing analysis report, analyzing signals at observe control points and capture control points of each of the critical paths for generating a plurality of test states, and transmitting the test states to a virtual instrumentation software architecture wrapper.

REFERENCES:
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 7036062 (2006-04-01), Morris et al.
patent: 2005/0154552 (2005-07-01), Stroud et al.

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