Method for performing a logic built-in-self-test in an...

Details Method for performing a logic built-in-self-test in an... Method for performing a logic built-in-self-test in an...

2011-03-22

2011-03-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

07913136

ABSTRACT:
The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps (10, 12) with the pseudo-random-pattern generator (26), deactivating the multiple-input-signature register (28), performing a functional update in order to propagate legal values into those storage elements (16), which require constrained values, activating or resetting (51) the multiple-input-signature register (28), and setting or programming a start value in a counter (42) for activating a loop back circuit (34) in order to avoid an overwriting of the well-constrained values in the storage elements (16).

REFERENCES:
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patent: 7721172 (2010-05-01), Wang et al.
“New Approach Moves logic BIST into Mainstream” by Kapur et al. Published in EETimes Oct. 14, 2002.
Yung-Chieh Lin; Feng Lu; Kai Yang; Kwang-Ting Cheng; , “Constraint extraction for pseudo-functional scan-based delay testing,” Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific , vol. 1, no., pp. 166-171 vol. 1, Jan. 18-21, 2005 doi: 10.1109/ASPDAC.2005.1466151.
“Built-In Constraint Resolution”, Grady Giles, Joel Irby, Daniela Toneva, and Kun-Han Tsai, International Test Conference, IEEE, 2005.
“Testing Digital Circuits with Constraints” Al-Yamani, Mitra, and McCluskey, CRC Technical Report, IEEE, 2002.

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