Method for patterning a polysilicon gate in deep submicron techn

Details Method for patterning a polysilicon gate in deep submicron techn Method for patterning a polysilicon gate in deep submicron techn

1998-10-01

2000-12-05

Thomas, Tom

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

By application of corpuscular or electromagnetic radiation

438636, 438689, 438706, 438717, 438725, 438729, 438952, 156643, 156656, 216 37, 216 42, 216 47, 216 72, 216 79, H01L 2126

Patent

active

061566292

ABSTRACT:
A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.

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