Method for optimizing loop bandwidth in delay locked loops

Details Method for optimizing loop bandwidth in delay locked loops Method for optimizing loop bandwidth in delay locked loops

2002-02-14

2004-02-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C327S147000, C327S150000

Reexamination Certificate

active

06687881

ABSTRACT:

BACKGROUND OF INVENTION
To increase processor performance, clock frequencies used by microprocessors, often referred to as “CPUs”, have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as power, switching noise, and signal integrity must be taken into account.
Higher frequencies for an increased number of circuits also increase switching noise on the power supply. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. The switching noise may have a local or global effect. Circuits that create large amounts of noise may be relatively isolated; however, they may also affect other circuits, possibly involving very complex interactions between the noise generation and the function of affected circuits. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock is often sent to help recover the data. The clock determines when the data should be sampled by a receiver's circuits.
The clock may transition at the beginning of the time the data is valid. The receiver would prefer, however, to have a signal during the middle of the time the data is valid. Also, the transmission of the clock may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1
shows a section of a typical computer system component (
10
). Data (
22
) that is ‘n’ bits wide is transmitted from circuit A (
20
) to circuit B (
40
). To aid in the recovery of the transmitted data, a clock composed of a clock signal (
30
), or CLK, is also transmitted with the data. The circuits could also have a path to transmit data from circuit B (
40
) to circuit A (
20
) along with an additional clock (not shown). The clock signal (
30
) may transition from one state to another at the beginning of the data transmission. Circuit B (
40
) requires a signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (
30
) may have degraded during transmission. The DLL has the ability to regenerate the clock signal (
30
) to a valid state and to create a phase shifted version of the clock to be used by other circuits, for example, a receiver's sampling signal. The receiver's sampling signal determines when the input to the receiver should be sampled.
One common performance measure for a DLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, the output plus a known phase shift, should track the input. In a repeated output pattern, such as a clock signal, a transition that occurs from one state to another that does not happen at the same time relative to other transitions is said to have jitter. Jitter is related to power supply noise.
Delay locked loops are basically first order feedback control systems. As such, the delay locked loop can be described in the frequency domain as having a loop gain and a loop bandwidth. The loop bandwidth is the speed at which a signal completes the feedback loop of the delay locked loop to produce an update (i.e., error signal). Ideally, the DLL should have the highest possible bandwidth so that the clock and data track each other. Power supply noise will, however, have a certain noise-versus-frequency characteristic that may require the loop bandwidth to be reduced to attenuate the effects of the power supply noise. The loop bandwidth determines to a large degree what portion of power supply noise is translated to output jitter.
Often, power supplied to a computer system component varies due to switching by active circuits, which in turn, affects the integrity of the component's output. Typically, this power variation results from parasitic inductance and/or resistance between a power supply for the component and the component itself. These effects may lead to the component not receiving power (via current) at the exact time it is required. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation.
FIG. 2
shows a section of a typical power supply network (
100
) of a computer system. The power supply network (
100
) may be representative of a single integrated circuit, or “chip”, or equally an entire computer system comprising multiple integrated circuits. The power supply network (
100
) has a power supply (
112
) that includes a power supply line (
114
) and a ground line (
116
) through an impedance network Z
1
(
118
). Impedance networks are a collection of passive elements that result from inherent resistance, capacitance, and/or inductance of physical connections. A power supply line (
122
,
123
) and a ground line (
124
,
125
) facilitate power supply to a circuit A (
120
) and circuit B (
126
), respectively. Power supply line (
123
) and ground line (
125
) also supply circuit C (
130
) through another impedance network Z
2
(
128
) and additional impedance networks and circuits, such as impedance network Z
n
(
132
) and circuit N (
134
). The impedance networks and connected circuits may be modeled in simulation so that the designer can better understand the behavior of how the circuits interact.
Still referring to
FIG. 2
, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may be analog or digital circuits. Also, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may generate and/or be susceptible to power supply noise. For example, circuit C (
130
) may generate a large amount of power supply noise that affects the operation of both circuit B (
126
) and circuit N (
134
). The designer, in optimizing the performance of circuit B (
126
) and circuit N (
134
), requires an understanding of the characteristics of the power supply noise.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for optimizing loop bandwidth in a delay locked loop comprises inputting a representative power supply waveform having noise to a simulation of the delay locked loop, estimating jitter of the delay locked loop, adjusting the loop bandwidth of the delay locked loop, and repeating the inputting, estimating, and adjusting until the jitter falls below a selected amount.
According to another aspect of the present invention, a computer system for optimizing loop bandwidth in a delay locked loop comprises a processor, a memory, and software instructions stored in the memory adapted to cause the computer system to input a representative power supply waveform having noise into a simulation of the delay locked loop, estimate jitter of the delay locked loop, adjust the loop bandwidth of the delay locked loop, and repeat the input, estimate, and adjust until the jitter falls below a selected amount.
According to another aspect of the present invention, a computer-readable medium that has recorded instructions thereon executable by a processor, where the instructions are adapted to input a representative power supply waveform having noise into a simulation of a delay locked loop, estimate jitter of the delay locked loop, adjust the loop bandwidth of the delay locked loop, and repeat the input, estimate, and adjust until the jitter falls below a selected

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