Method for optimizing a set of scan diagnostic patterns

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

06996791

ABSTRACT:
A method and system for generating a set of scan diagnostic patterns for diagnosing fails in scan chains. The method including: (a) selecting a set of latches; (b) selecting a pattern from a set of test patterns; (c) determining the number of lateral insertions of the selected pattern; (d) determining a number of new lateral insertions that the selected pattern would add to the set of scan diagnostic pattern and adding the selected pattern and a corresponding new insertion count to a count list; (e) repeating steps (b) through (d) until all patterns of the set of test patterns have been selected; (f) selecting a pattern from the count list; (g) adding the pattern selected from the count list to the set of scan diagnostic patterns; and (h) repeating steps (b) through (g) until a there are a predetermined number of patterns in the set of scan diagnostic patterns.

REFERENCES:
patent: 5903466 (1999-05-01), Beausang et al.
patent: 2003/0023941 (2003-01-01), Wang et al.

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