Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2000-02-09
2001-06-05
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S507000
Reexamination Certificate
active
06242325
ABSTRACT:
The present invention concerns the field of integrated circuit manufacturing and, more particularly, methods for optimising the etching rate of a polycrystalline layer to be deposited and etched during the manufacture of integrated circuits.
During a conventional integrated circuit manufacturing process, a stack of thin layers is formed on a semi-conductor substrate such as silicon. One will recall that there are three categories of chemical species to be considered in such a material: residual impurities such as the oxygen and carbon in the silicon, the doping impurities and, possibly, deliberately implanted impurities, for example during hydrogenation of a polycrystalline silicon layer.
Essentially, two types of deposition technique for forming a thin layer on a substrate can be distinguished. The so-called “physical” techniques are based on growth by condensation of molecular or atomic beam (neutral or ionised) on a substrate, these beams of particles being obtained by evaporation or sputtering from a source. Thus one speaks of deposition by vacuum evaporation, by cathodic sputtering, or molecular beam epitaxy. Furthermore, the so-called “chemical” techniques are based on a chemical reaction at the surface of the substrate, or of the layer which is in the process of being formed. This reaction releases chemical species which will intervene to assure or continue the growth of the layer. One thus speaks of deposition by liquid-phase or vapour-phase epitaxy.
In the rest of the process, the polycrystalline layers thereby formed are etched by wet process or dry process, via the action of a reactive agent. The current tendency veers towards dry process etching techniques, in particular plasma etching and, in particular, RIE (Reactive Ion Etching). One will recall that a plasma is a gas heated to a high temperature, rich in ions and free electrons. In a plasma etching reactor, electroluminescent discharges are produced at low pressure, and generate chemically active species. These species combine with each other at the surface of a layer placed in the reactor to be etched therein. During such etching, volatile compounds are formed and evacuated by a pumping system.
By way of example, etching of aluminium is achieved by a plasma formed of a chlorine gas such as BC13, said reactive agent being the chlorine. In this case, the presence of a gas such as BC13 is necessary to eliminate the native surface oxide, this oxide not being etched by pure chlorine.
In the present description, an etching rate, which can be defined as the ratio of the average etched thickness to the etching time necessary to perform such etching, is associated with an etching method.
Within the field of microelectronics, polycrystalline layers are used, for example for making electrical contacts. By way of example, the materials frequently used to form such layers include aluminium, silicon or silicides. One will recall that a silicide is a compound based on silicon and refractory materials such as tungsten, titanium or molybdenum.
Generally, a polycrystalline layer is formed of a mosaic of crystals or “grains”, i.e. a periodic lattice network characterised by an elementary lattice, in which there exists a minimum number of crystallographic faults such as breaks in periodicity and residual impurities. One will recall that a polycrystalline layer is formed of grains attached along contact lines called “grain boundaries”.
Given that the growth of a polycrystalline layer corresponds to the thermodynamic conditions giving rise to a nucleation phenomenon around a critical core, the maximum size of a grain is limited by the presence of a neighbouring grain. In other words, to the extent that the distribution of the critical cores is homogenous, so is that of the grain size of a polycrystalline layer formed by nucleation around such cores, and the sizes of such grains regroup around an average value, with very slight dispersion. One can thus define the average and the dispersion of the grain size of a polycrystalline layer, which will be designated respectively &mgr; and &sgr; in the following description.
The Applicant of the present invention has noted that the structure of a polycrystalline layer is not generally taken into account during etching of such layer. In other words, account is usually taken of the macroscopic features of the layer to be etched, for example the thickness thereof.
Moreover, within the extremely competitive field of microelectronics, one of the main concerns lies in permanent research into reducing the manufacturing time for integrated circuits, and increasing the yield of the technical installations used during such manufacturing.
An object of the present invention is to provide a method for optimising the deposition and etching processes implemented during manufacturing of integrated circuits, this method being capable of increasing the yield of etching related equipment.
Another object of the present invention is to provide such processes answering conventional industrial cost and complexity criteria.
These objects, in addition to others are achieved by the optimisation method according to claim
1
.
An advantage in determining the deposition parameters in the optimisation method according to the present invention is the ability to form a polycrystalline layer in which the density of the grain boundaries is linked to an optimum value of the etching rate, having the effect of increasing this rate, which translates into an increase in the yield of the etching related equipment.
REFERENCES:
patent: 4561907 (1985-12-01), Raicu
patent: 4892844 (1990-01-01), Cheung et al.
patent: 5322712 (1994-06-01), Norman et al.
patent: 5344793 (1994-09-01), Zeininger et al.
Lecohier Baudouin
Schönbächler Edgar
Christianson Keith
EM Microelectronic-Marin SA
Griffin & Szipl, P.C.
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