Method for operating a memory

Details Method for operating a memory Method for operating a memory

1998-02-19

1999-12-21

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 1500

Patent

active

060058110

ABSTRACT:
A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the effective page cycle time. The multiple page memory of this invention is very effective in graphics applications where multiple page memory access is required. A memory with multiple page random access in accordance with this invention greatly enhances performance by allowing different sources to continue to access the memory in the page mode, in spite of intervening memory accesses by other sources to other rows of the memory. A VRAM with multiple page random access in accordance with this invention provides an even higher performance graphic memory system.

REFERENCES:
patent: 4959811 (1990-09-01), Szczepanek
patent: 4961171 (1990-10-01), Pinkham
patent: 5088062 (1992-02-01), Shikata
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5179372 (1993-01-01), West et al.
patent: 5206833 (1993-04-01), Lee
patent: 5210723 (1993-05-01), Bates et al.
patent: 5530955 (1996-06-01), Kaneko

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