Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-07-24
2004-04-27
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189011
Reexamination Certificate
active
06728147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for on-chip testing of memory cells of a cell array of an integrated memory circuit, in particular of a RAM (Random Access Memory) or a DRAM (Dynamic Random Access Memory). Different data patterns are written to memory cells and read from the memory cells for testing purposes. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller for data control.
Integrated memory circuits realized on semiconductor chips are subjected to tests and repair processes even when they are still on the wafer, in order to determine the quality of the chip, and in order to exclude or repair chips, if appropriate, before continuing with further production steps. For this purpose, in a test mode, test data patterns are written to the cell arrays of the memory circuit and are thereupon read out and checked with regard to their content. By way of example, crosstalk between adjacent memory cells may prove to be critical, for which reason different data patterns, for example, are written to such memory cells.
The above-described method is known for example as a so-called “March” test, which provides for the basic data pattern to be stored in a data register and to be written in a targeted manner to a memory cell to be tested. In the next step, the basic data pattern is firstly inverted and written as inverted basic data pattern to another memory cell to be tested, for example to that cell which is an adjacent cell relative to the first-mentioned memory cell to which the basic data pattern has been written. This test sequence is relatively time-consuming on account of the access and reloading steps required. Moreover, on the basis of the basic data pattern, it only allows the generation of an inverse data pattern with respect thereto for test purposes, so that the data topology available for the test is greatly restricted and is thus meaningful only to a limited extent.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for on-chip testing which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which proceeds more rapidly and whose results are more sound and meaningful than the results of conventional methods.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for on-chip testing of memory cells of a cell array of an integrated memory circuit, the method includes the steps of:
writing different data patterns including a basic data pattern and at least one further data pattern different from the basic data pattern to memory cells and reading the different data patterns from the memory cells in order to test the memory cells;
storing the basic data pattern in a data word register and reading out the basic data pattern by applying a data control signal provided by a controller for data control; and
storing the at least one further data pattern in a data word register section and accessing, with the data control signal, in addition to accessing the basic data pattern, the at least one further data pattern in a targeted manner.
In other words, a method for on-chip testing of memory cells of a cell array of an integrated memory circuit, in particular of a RAM or DRAM, in which, for test purposes, different data patterns are written to memory cells and read from the latter, of which a basic data pattern is stored in a data word register and read out by application of a data control signal provided by a controller for data control, includes accessing, through the use of the data control signal (DCTL), in addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, in a targeted manner.
In contrast to the method according to the prior art, which provides a test sequence with inversion and frequent reloading of the basic data pattern, the method according to the invention operates on the basis of a plurality of data patterns which can be directly accessed at any time without inversion and reloading. This is advantageous firstly in respect of time and secondly on account of the complex data topology available as a result. It is advantageous, moreover, that the relatively complex data topology can be accessed in a simple manner through the use of the data control signal which, heretofore, has been utilized inter alia for the inversion of the basic data pattern.
More specifically, in accordance with the test method according to the invention, it is provided that through the use of the data control signal, in addition to the basic data pattern, at least one further data pattern which differs from the basic data pattern and is stored in a data word register section is accessed in a targeted manner.
Proceeding from the conventional method sequence with an inversion of the basic data pattern, the method sequence according to the invention is downward compatible since the functionality of the previous method sequence or of the associated hardware is maintained if the data control signal does not load the data pattern which differs from the basic data pattern.
The complexity of the test data topology that can be attained according to the invention can be extended as desired without thereby increasing the test time duration. Proceeding from the basic idea according to the invention, namely of providing a further data pattern independent of the basic data pattern in a manner that allows access through the use of the data control signal, it is provided for this purpose that a plurality of data patterns which differ from the basic data pattern and also differ with respect to one another are stored in a corresponding plurality of data word register sections.
The data word register sections discussed can be implemented in hardware in various ways. Thus, it may on the one hand be provided that the basic data pattern and the data pattern or data patterns which differs or differ from it are stored in separate data word registers. As an alternative to this, it may be provided that the basic data pattern and the data pattern or data patterns which differs or differ from it are stored in data word register sections of a common complex data word register.
In the case where the data word register sections are implemented in separate data word registers, a multiplexer circuit is advantageously provided whose inputs are connected to the outputs of the data word registers in order to apply the data patterns in a targeted manner to memory cells to be tested.
In the case where the data word register sections are implemented in a common complex data word register, it is advantageously provided that the complex data word register has a plurality of outputs in accordance with the plurality of data patterns for separately outputting the data patterns, and in that the data control signal is applied to a multiplexer circuit whose inputs are connected to the outputs of the complex data word register in order to apply the data patterns in a targeted manner to memory cells to be tested.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for on-chip testing of memory cells of an integrated memory circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
REFERENCES:
patent: 4757503 (1988-07-01), Hayes et al.
patent: 4805093 (1989-02-01), Ward
patent: 6198669 (2001-
Beer Peter
Kallscheuer Jochen
Krause Gunnar
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran M.
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