Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-04
2004-05-04
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S308000, C438S920000
Reexamination Certificate
active
06730566
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor processing and, more particularly, to a method for non-thermally nitrided gate formation for high voltage devices.
BACKGROUND OF THE INVENTION
In certain semiconductor applications it has become necessary to integrate dual gate oxide (DGO) thicknesses for associated transistor devices onto a single integrated circuit device. One motivation for performing dual gate oxide processing is that high performance transistors require thinner gate dielectric regions and operate at lower voltages (e.g., 1.8 volts to 2.5 volts), where as devices that interface with most conventional external peripherals typically require higher operating voltages such as 3.3 volts to 5.0 volts. When interfacing lower voltage high performance metal-oxide-semiconductor field-effect-transistors (MOSFETs), within a core of an integrated circuit, to higher voltage peripheral devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages.
For example, current microcontroller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single integrated circuit, such as high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies onto a single circuit die. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses to provide both high performance lower voltage devices within the core of the device and higher voltage I/O devices to interface with external peripheral devices.
As stated above, a dual gate thickness structure includes thin gates for high performance, low voltage operation core devices and thick gates for low leakage, high voltage operation I/O devices. As devices shrink, even the thick gates are getting thinner to meet device requirements. This can cause increased leakage current at the thick gate oxides. The leakage current can be mitigated by introducing nitrogen atoms into the gate dielectrics to suppress leakage currents for both the thin and thick gates. One method of nitrogen atom introduction is to perform non-thermal nitridation (e.g., plasma nitridation) on the gate dielectrics. However, the nitridation introduces damage (e.g., plasma damage) to the top surface of the gate dielectrics resulting in a porous surface layer. The damage can cause high gate leakage, threshold voltage shifts, or premature oxide breakdown when the devices are operating. A post-nitridation high temperature (e.g., at or above 1000° C.) re-oxidation (HT ReOx) can be performed on the gate dielectrics to mitigate the plasma damage from the gate dielectrics. However, due to the high thermal treatments, the gate dielectrics will densify, providing strong Si—N bonding in the dielectrics. This is an issue for deglaze of the I/O gates causing longer etching time resulting in over-etch issues at the isolation regions (e.g., standard trench isolation (STI) comer oxide).
Film densification and etching time can be minimized by omitting the post nitridation high temperature re-oxidation during the process. However, omission of the post nitridation high temperature re-oxidation results in gate layers that have damage (e.g., plasma damage) causing a superficial porous layer that results in less than optimal device operation. Additionally, in a subsequent photoresist removal process, the strong photoresist stripping material removes nitrogen atoms from the I/O gate dielectrics due to the looser chemical bonds in the damaged surface layer.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a method for non-thermally nitrided gate formation of high voltage transistor devices (e.g., 3.3 volts to 5.0 volts). The present invention is particularly useful in the formation of dual thickness gate dielectric structures that include thick gates (e.g., about 15 Å to about 35 Å oxide layer) for high voltage transistor devices and thin gates (e.g., about 8 Å to about 14 Å oxide layer) for low voltage transistor devices (e.g., 1.8 volts to 2.5 volts). The non-thermally nitrided gate formation comprises nitridation, for example, by plasma nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices. The nitridation of the gate dielectric layer damages (e.g., plasma damage) the surface of the gate dielectric layer. The damage to the surface of the gate dielectric layer is removed by a relatively low temperature (e.g., about 400° C. to about 600° C.) re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process, and mitigates film densification, such that the gate dielectric can be readily etched by standard etching chemicals in subsequent processing.
REFERENCES:
patent: 5960289 (1999-09-01), Tsui et al.
patent: 5989962 (1999-11-01), Holloway et al.
patent: 6171911 (2001-01-01), Yu
patent: 6268272 (2001-07-01), Jang
patent: 6287897 (2001-09-01), Gousev et al.
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6335262 (2002-01-01), Crowder et al.
Alshareef Husam N.
Khamankar Rajesh
Niimi Hiroaki
Brady III Wade James
Dang Phuc T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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