Method for narrow space formation and self-aligned channel impla

Details Method for narrow space formation and self-aligned channel impla Method for narrow space formation and self-aligned channel impla

1996-12-31

1999-06-29

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438197, 438199, 438585, 438299, H01L 21336

Patent

active

059181320

ABSTRACT:
A method of forming a narrow space using a litho-less process is disclosed. A first mask is formed on a substrate, the first mask having an edge. A spacer is then formed adjacent to the edge. A second mask is subsequently formed adjacent to the spacer. The spacer is then removed.

REFERENCES:
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5472897 (1995-12-01), Hsu et al.
patent: 5489543 (1996-02-01), Hong
patent: 5534447 (1996-07-01), Hong
patent: 5538913 (1996-07-01), Hong
Fiegna et al, "Scaling the MOS Transistor Below 0.1 um: Methodology, Device Structures, and Technology Requirements", TED Jun. 1995, p. 941.
Kimura et al, "Short-Channel-Effect-Supressed Sub 0.1 um Grooved-Gate MOSFET's with W Gate", TED Jan. 1995, p. 94.
J. T. Jhorstmann et al, "Characterizatin of Sub-100 nm-MOS Transistors Fabricated by Optical Lithographer and a Sidewall-Etchback Process" NME, Sep. 1995.

Affiliated with

Also associated with

Rating

Method for narrow space formation and self-aligned channel impla does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for narrow space formation and self-aligned channel impla, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for narrow space formation and self-aligned channel impla will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1386446