Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1995-12-29
2000-10-17
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
061346837
ABSTRACT:
In a telecommunication network of ATM exchanges (V1, Vn) via which information transmitted in the STM mode can also be switched, error-detecting code words (EDCE) are respectively derived at an exchange input (EVi) from the content of information parts (PL) of a defined plurality of ATM cells in order to monitor the through-connections through an exchange. These error-detecting code words (EDCE) are transmitted to an exchange output in transition monitoring cells (DUZ) together with the plurality of information parts (PL) and are compared thereat to a newly formed error-detecting code word.
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Clark Mark
Hoffmann Robert
Beausoliel, Jr. Robert W.
Elisca Pierre Eddy
Siemens Aktiengesellschaft
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