Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-28
2004-06-29
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06756275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for manufacturing read only memory (ROM) devices. More specifically, a method is disclosed for minimizing the product turn-around time for making semiconductor permanent store ROM cells with small cell size. This invention particularly involves the use of boron implantation through single or multi-level metal interconnections, which are formed within a ROM region.
2. Description of the Prior Art
Read-only memory (ROM), also known as firmware, is an integrated circuit programmed with specific data when it is manufactured. ROM chips are used not only, in computers, but in most other electronic items as well. The process of programming data is also referred to as coding. Hitherto, numerous coding methods have been developed to program data into the memory cells during different phases of their manufacture. One development that has gained wide use is the threshold voltage implant method, which changes a transistor's threshold voltage by ion implanting the transistor gates for programmed cells. By way of example, for coding an N-channel memory cell, a predetermined dosage of impurities such as boron are implanted into the channel area under the gate of the transistor to raise its threshold voltage, thereby turning this memory cell into an “off” state.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter part of the process, it takes less time to complete wafer processing. Customers require the product turn-around time between receipt of the ROM code for a custom order and delivery of finished parts to be kept as short as possible. Less time for completion means a shorter product turn-around time.
U.S. Pat. No. 4,268,950, filed Jun. 5, 1978 by Chatterjee et al., assigned to Texas Instruments discloses a process for making an N-channel silicon gate MOS read only memory that may be programmed at a late stage in the manufacturing process. The cell array is programmed by boron implantation through a protective nitride, polysilicon strips, and gate oxides to raise the threshold voltage of selected cells to a value above that which will be turned on by the voltage on the selected address line. According to U.S. Pat. No. 4,268,950, no metal lines are used in the cell array, only in the peripheral areas.
U.S. Pat. No. 5,514,609, filed May 13, 1994 by Chen et al., assigned to Mosel Vitelic discloses the manufacture of a ROM cell that is coded before metallization. ROM code impurities are implanted first through a dielectric layer overlying gate electrodes, and then through the underlying selected gate electrodes.
U.S. Pat. No. 6,020,241, filed Dec. 22, 1997 by You et al., assigned to Taiwan Semiconductor Manufacturing Company discloses a method of manufacturing a ROM that is code implanted late in the process after the first level metal thus reducing the turn-around time to ship a customer order. It is noted that the first level metal is not formed in the cell areas, but is formed over the peripheral areas. The code implantation implants impurities through a first dielectric layer overlying gates and a second dielectric layer overlying the first dielectric layer, and through a portion of the word lines.
For today's high-density ROM device, to reach a highest packing density, some metal interconnections such as bit lines are inevitably formed within the memory array area overlying word lines, instead of buried diffusion bit lines in the substrate as disclosed in the prior art, which occupy a lot of chip area. However, none of the above-mentioned prior art references teaches a method capable of coping with difficulties that occur when coding a ROM integrated circuit device having multilevel metal interconnections formed within the ROM region or cell array area while maintaining a short product turn-around time.
SUMMARY OF THE INVENTION
It is therefore a primary objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that may be programmed at a selected level of multilevel metal interconnections that are formed within the ROM region, thereby shortening the product turn-around time.
It is a further objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that involves the use of relatively high energy ion implantation to program selected transistors though multilevel metal interconnections, Inter-layer dielectric (ILD), polysilicon gates, and gate oxides.
Briefly summarized, the preferred embodiment of the present invention discloses a method for manufacturing a read only memory (ROM) device capable of shortening product turn-around time. The ROM device includes a semiconductor substrate having thereon an array of enhancement-mode metal-oxide-semiconductor field-effect transistors (MOSFETs) within a ROM region and a first dielectric layer covering the MOSFETs within the ROM region. Each of the MOSFETs has a polysilicon gate, a source, a drain, and a gate oxide between the polysilicon gate and the substrate. All of the MOSFETs are initially in a logic “0”, state at a first threshold voltage. After planarizing the first dielectric layer, m layers of metal interconnections are formed over the first dielectric layer within the ROM region. According to the first preferred embodiment of the present invention, the top layer of the m layers of metal interconnections (m-th layer metal) within the ROM region is further covered by a top inter-metal dielectric (IMD) layer corresponding to the IMD layer of the m+1 layer metal interconnection that is fabricated in the peripheral area. According to the second preferred embodiment of the present invention, the top layer of the m layers of metal interconnections is covered by a plurality of IMD layers each of which corresponds to one of the IMD layers from the m+1 layer to the Xth layer metal interconnections that are fabricated in the peripheral area.
In accordance with the first preferred embodiment of the present invention, the method generally includes the steps of: forming a mask layer on the top IMD layer, the mask layer having an opening exposing the entire ROM region; etching away a thickness of the top IMD layer through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region; removing the mask layer; forming a coding photoresist layer on the remaining top IMD layer in the recess; patterning the coding photoresist layer to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic “0” state into a logic “1” state; using the patterning coding photoresist layer as an implant hard mask to implant the underlying MOSFETs to be coded through the apertures, m layers of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby transforming the MOSFETs to be coded into the logic “1” state at a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage; and stripping the coding photoresist layer.
In accordance with the second preferred embodiment of the present invention, the method includes forming a mask layer on the plurality of IMD layers. The mask layer has an opening exposing the entire ROM region. A thickness of the plurality of IMD layers is etched away through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region. The mask layer is removed. A coding photoresist layer is formed on the remaining top IMD layer in the recess. The coding photoresist layer is then patterned to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic “0” state into a logic “1” state. The patterning coding photoresist layer is used as an implant hard mask to implant the underlying MOSFETs to be coded through the apertu
Chen Chih-Hung
Cheng An-Ru
Liu Kwo-Jen
Blum David S.
Chaudhari Chandra
Faraday Technology Corp.
Hsu Winston
LandOfFree
Method for minimizing product turn-around time for making... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for minimizing product turn-around time for making..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for minimizing product turn-around time for making... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3304110