Method for minimizing ground bounce during DC parametric tests u

Details Method for minimizing ground bounce during DC parametric tests u Method for minimizing ground bounce during DC parametric tests u

1997-10-23

1999-12-07

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714726, G01R 3128

Patent

active

060000503

ABSTRACT:
The method of controlling ground bounce during DC parametric tests disclosed herein is based on the formulation of tests that best achieve two broad goals. The first goal is to reduce the number of I/O pins that are switched simultaneously. In the formulation of the VIL and VIH tests this goal is implemented by preferably only switching one input at a time. The second goal is to simultaneously switch I/O pins that are distant from one another. In the formulation of the VOL and VOH tests this goal is implemented by partitioning the outputs into subsets and selecting preferably one and only one output at a time from each and every subset.

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