Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-07-09
2001-04-17
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S394000, C430S396000
Reexamination Certificate
active
06218079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming a metal wiring using a dual damascene process.
2. Description of the Related Art
With an increase in the integration of semiconductor devices, a multi-layered metal wiring structure is required, and the spacing between metal wirings has decreased. Thus, the parasitic resistance (R) effect and the parasitic capacitance (C) effects existing between adjacent conductors on a layer and between vertically adjacent wiring layers are potentially greater for highly-integrated semiconductor devices. Such parasitic resistance and capacitance degrade the electrical performance of the device due to a delay induced by RC. Also, the parasitic resistance and capacitance components increase the overall chip power dissipation and the amount of signal cross talk. Therefore, in ultra highly-integrated semiconductor devices, it is important to develop a technology of multi-layered wiring having a small RC.
In order to form a high performance multi-layered wiring structure having a low RC, a wiring layer must be formed of a metal having low resistivity and/or a dielectric layer having low permittivity must be used.
In order to lower the resistance in the metal wiring layer, research is actively being conducted into using a metal having low resistivity, e.g., copper, to form the metal wiring layer. But it is difficult to obtain a copper wiring by directly patterning a copper film using photolithography. Thus, a dual damascene process is usually used to form the copper wiring.
Also, in order to reduce the capacitance generated between the metal wiring layers, a technique of using a low dielectric film as an interlayer dielectric film between the metal wirings has been developed.
In the prior art, however, even if the low dielectric film is used as the interlayer dielectric film, a film formed of a material having relatively high permittivity such as a silicon nitride or a silicon oxynitride is used as a mask layer for patterning the interlayer dielectric film during the dual damascene process. As a result, the high permittivity mask layer remains between the interlayer dielectric film even after the device is completed, thus increasing the mean permittivity of the interlayer dielectric film. Consequently, the advantage of using the low dielectric film as the interlayer dielectric film is reduced.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method of forming a metal wiring using a dual damascene process, by which capacitance generated between multi-layered metal wirings in a semiconductor device can be minimized.
Accordingly, a first interlayer dielectric film is formed on a semiconductor substrate on which a conductive layer is formed. A photosensitive polymer pattern having a first hole that has a first width and exposes the upper surface of the first interlayer dielectric film is formed on the first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern and the exposed first interlayer dielectric film. A mask pattern having a second hole which is located directly above the first hole, has a second width larger than the first width, and exposes the second interlayer dielectric film, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.
The first and second interlayer dielectric films are each formed of a material selected from the group consisting of hydrogen silsesquioxane (HSQ), SiO
2
, SiCO, amorphous carbon, amorphous CF, porous silica, parylene, and combination thereof.
The step of forming the photosensitive polymer pattern comprises the sub-steps of forming a photosensitive polymer film on the first interlayer dielectric film, and forming the photosensitive polymer pattern by exposing and developing a predetermined portion of the photosensitive polymer film.
The photosensitive polymer film is made of a material selected from the group consisting of polyolefin, polyacetal, polycarbonate, polypropylene and polyimide.
The mask pattern is formed of a photoresist or photosensitive polymer.
The step of forming the wiring region and the step of forming the via hole region can be consecutively performed as a single etching step.
After the step of forming the via hole region, the following steps can be further comprised: the step of removing the mask pattern, and the step of forming a wiring layer within the wiring region and simultaneously forming a via contact within the first hole and the via hole region for electrically connecting the semiconductor substrate to the wiring layer, by depositing a conductive material to fill the via hole region and the wiring region.
The conductive material is a material selected from the group consisting of aluminum, tungsten, copper and alloys thereof.
The step of forming a barrier layer on the second interlayer dielectric film, and on the photosensitive polymer pattern and the first interlayer dielectric film where they are exposed by the wiring region and the via hole region can be further comprised before the conducive material is deposited. Here, the conductive material is deposited on the barrier layer. The barrier layer is formed of a material selected from the group consisting of Ta, TaN and TiN.
The step of planarizing the upper surface of the wiring layer by chemical mechanical polishing (CMP) can be further comprised after the step of forming the via contact. Here, the barrier layer on the second interlayer dielectric film is removed by the CMP.
According to another embodiment of the present invention, a first interlayer dielectric film is formed on a semiconductor substrate on which a conductive layer is formed. An etch stop layer is formed on the first interlayer dielectric film. A second interlayer dielectric film is formed on the etch stop layer. A photosensitive polymer pattern having a first hole which has a first width and exposes the second interlayer dielectric film is formed on the second interlayer dielectric film. A photoresist pattern having a second hole which has a second width smaller than the first width and exposes the second interlayer dielectric film is formed on the upper surface of the second interlayer dielectric film exposed through the photosensitive polymer pattern and the first hole. A third hole, defining a second interlayer dielectric film pattern and an etch stop layer pattern, which expose a region of the first interlayer dielectric film through the second hole and the third hole having the same width as the second hole, are formed by sequentially dry-etching the exposed second interlayer dielectric film and the etch stop layer using the photoresist pattern as an etch mask. The photoresist pattern is removed. A wiring region and a via hole region are simultaneously formed by dry-etching the first and second interlayer dielectric films using the photosensitive polymer pattern and the etch stop layer pattern as an etch mask.
The first and second interlayer dielectric films are each formed of a material selected from the group consisting of hydrogen silsesquioxane (HSQ), SiO
2
, SiCO, amorphous carbon, amorphous CF, porous silica, parylene, and combination thereof.
The etch stop layer is formed of SiC or photosensitive polymer.
The step of forming the photosensitive polymer pattern comprises the substeps of: forming a photosensitive polymer film on the second interlayer dielectric film; and forming the photosensitive polymer pattern by exposing and developing a predetermined portion of the photosensitive polymer film.
The photosensitive polymer film is made of a material selected from the group consisting of polyolefin, polyacetal, polycarbonate, polypropylene and polyimide.
The
Kim Byeong-Jun
Shin Hong-jae
Baxter Janet
Gilmore Barbara
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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