Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-06-27
2004-04-13
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S205000
Reexamination Certificate
active
06721217
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to methods for sensing data stored in memory cells in memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric memory devices, and other type semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells include capacitors constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complimentary bitline and a plateline signal voltage, and interrogating the cell. There are several techniques to interrogate a FeRAM cell. Two most common interrogation techniques are step sensing and pulse sensing. In both these interrogation techniques, the cell capacitor is coupled to the complimentary bitline by turning ON an access or a pass gate. In the step sensing, the plateline voltage is stepped from ground (Vss) to a supply voltage (Vdd). In the pulse sensing the plateline voltage is pulsed from Vss to Vdd and then back to Vss. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (V
“0”
) associated with a capacitor programmed to a binary “0” and that of the capacitor programmed to a binary “1” (V
“1”
). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local IO lines.
The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bitlines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bitlines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bitline, and a sense amp senses the differential voltage across the bitlines and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”.
In modern memory devices having millions of data cells, there is a continuing need to reduce component sizes and otherwise to conserve circuit area in the device, so as to maximize device density. Accordingly, memory cell layout architectures such as folded bit configurations have been developed to conserve on the amount of die area needed to implement large scale memories, like 64 megabit devices. Such devices are typically divided internally into blocks, sections, segments, rows and columns. For example, a 64M device may include 8 blocks of 8M each, each block may consist of 8 sections of 1M each, each section may be 32 segments, with each segment containing 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each column is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
FIG. 1
schematically illustrates a segment portion of a memory device
2
having 512 rows (words) and 64 columns (bits) of data storage cells C
ROW-COLUMN
configured in a folded bitline architecture, where each column of cells is accessed via a pair of complimentary bitlines BL
COLUMN
and BL
COLUMN
′. One column of the device
2
is illustrated in FIG.
2
. The cells C
1
-
1
through C
1
-
64
form a data word accessible via a wordline WL
1
and complimentary bitline pairs BL
1
/BL
1
′ through BL
64
/BL
64
′, where cell data is sensed during data read operations using sense amp circuits S/A C
1
through S/A C
64
associated with columns
1
through
64
, respectively. In a typical folded bitline architecture ferroelectric memory device, the cells C
ROW-COLUMN
individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bitlines associated with the cell column and a plateline, where the other bitline is connected to a reference voltage.
In the device
2
, the sense amps associated with even numbered columns are located at the bottom of the segment, whereas sense amps associated with odd numbered columns are located at the top of the segment. In order to reduce the number of components in the device
2
, as well as to increase device density therein, individual reference voltage generators are not provided for each complimentary bitline pair. Rather, shared reference generators are provided at the top and bottom of the segment columns. An even column reference generator
8
is provided at the bottom of the segment columns to service the sense amps associated with even numbered columns and an odd column reference generator
8
′ is provided at the top of the segment columns to service the sense amps associated with odd numbered columns. The reference voltages from the generators
8
,
8
′ are coupled to one of the bitlines in the columns using one of a pair of switches
8
a
,
8
b
, depending upon whether an odd or even numbered target data word is being read.
Sharing the reference generators
8
,
8
′ across multiple data columns, however, requires the connection of reference bitlines from all the odd numbered columns to one another, and the connection of reference bitlines from all the even numbered data columns together through the activated switches
8
a
or
8
b
. In a standard ferroelectric memory read sequence, the complimentary bitlines are precharged or equalized to ground and then left floating. Then, sense bitlines (e.g., the ones of the complimentary bitlines associated with the cell to be accessed) are connected to the target data cells of interest and the cells are interrogated. The reference generators
8
,
8
′ are then connected to the reference bitlines (the others of the complimentary bitline pairs), so as to establish a differential voltage at the sense amp terminals.
However, due to the physical proximity of the complimentary bitlines to one another, the connection of the sense bitlines to the target cells causes corresponding voltages to be coupled to the floating reference bitlines. These coupled voltages on the reference bitlines depend upon the signal level
Madan Sudhir K.
McAdams Hugh
Auduong Gene
Brady III W. James
Keagy Rose Alyssa
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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