Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2003-04-01
2004-12-07
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000, C438S018000, C438S382000
Reexamination Certificate
active
06828164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a structure of measuring the etching speed and the associated method. In particular, the invention relates to a method of detecting the etching speed of a metal layer in a microelectromechanical system (MEMS) manufacturing process.
2. Related Art
In the manufacturing process of microelectromechanical system (MEMS) devices, some suspending structures (the infrared (IR) sensor, micro heater, gas sensor, and pressure sensor in sensors and the accelerator meter, micro motor, and gyroscope in actuators) are needed. The formation of such suspending structures is done by depositing a sacrifice layer, followed by stacking a structure layer, and finally etching the sacrifice layer to put the whole structure in a suspending state. Whether the suspending structure is perfect depends upon whether the etching is complete. The conventional judging method is to use a microscope or scanning electronic microscope (SEM) to view the etched part by naked eyes. However, the efficiency is not good so that such manufacturing process cannot satisfy the need for mass production. On the other hand, most structures that are checked using the microscope or SEM are limited to the cases where the structure layer stacked on the sacrifice layer is made of a transparent material. Thus, the conventional method does not apply to opaque materials. Moreover, in the MEMS manufacturing process, the etching speed control is also another important factor. The method of using the microscope or SEM has also a worse precision.
SUMMARY OF THE INVENTION
In view of the foregoing, the invention provides a structure and method for measuring the etching speed. An objecive of the invention is to use the relation between the etching time and the equivalent resistance of sensing resistors in the structure to compute the etching speed.
To achieve the above objective, the disclosed structure includes a test layer and a plurality of sensing resistors. The sensing resistors are connected to the test layer and adjacent resistors. When measuring the etching speed, the sensing resistors form a circuit and one measures their equivalent resistance.
The disclosed method includes the following steps: providing a test layer and a plurality of sensing resistors connected to the test layer and adjacent sensing resistors, forming a circuit from the sensing resistors for measuring its equivalent resistance during etching, and measuring the equivalent resistance of the sensing resistor and obtaining the corresponding etching depth and time, thereby computing the etching speed.
In consideration of errors of resistors resulted from the manufacturing process, the invention also provides a structure for measuring the etching speed. The structure includes a test layer, several sensing resistors, and several dummy resistors. The sensing resistors are connected to the test layer and adjacent resistors. When measuring the etching speed, the sensing resistors form a circuit and one measures their equivalent resistance. Each of the dummy resistors is close to the corresponding sensing resistor. The two ends of each of the dummy resistors are connected to the two ends of its adjacent dummy resistors and form a parallel circuit. When measuring the etching speed of the test layer, the dummay resistors are combined with the sensing equivalent resistance to generate a reference value. This reference value is used to obtain the relation betwen the time and etching depth, thereby computing the etching speed.
Finally, the invention also provides a method for measuring the etching speed according to the previously introduced structure. The method includes the following steps. First, a test layer and several sensing resistors are provided. The test layer and the adjacent sensing resistors are connected to form a parallel circuit for providing a sensing equivalent resistance. Several dummy resistors are then provided; each dummy resistor is next to the corresponding sensing resistor. When measuring the etching speed on the test layer, a dummy equivalent resistance is produced to, along with the sensing equivalent resistance, generate a reference value. Finally, the reference value is used to compute the relation between the time and etching depth, thereby obtaining the etching speed.
REFERENCES:
patent: 5439554 (1995-08-01), Tamura et al.
patent: 6649528 (2003-11-01), Yanagisawa et al.
Chen Stella Y. H.
Chiou Jing-Hung
Liang Chao-Chiun
Wang Chin-Horng
Yen Kai-Hsiang
Birch & Stewart Kolasch & Birch, LLP
Industrial Technology Research Institute
Nguyen Thanh
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