Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-05-23
2006-05-23
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S113000, C711S137000, C711S202000, C710S100000, C710S260000, C712S200000, C712S216000, C712S219000, C712S227000
Reexamination Certificate
active
07051177
ABSTRACT:
A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.
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Kurihara Toshihiko
Le Hung Qui
Mericas Alexander Erik
Mirabella Robert Dominick
Okuno Michitaka
Dillon & Yudell LLP
McBurney Mark E.
Sparks Donald
Truong Bao Q
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