Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Patent
1998-10-02
2000-10-24
Nelms, David
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
438 14, 438 17, 438468, 3241581, H01L 2166
Patent
active
061366196
ABSTRACT:
A method for measuring resistance changes is described to study electromigration induced failures in conductive patterns. This method can provide a basis for lifetime predictions based on low value failure criteria, i.e. small resistance changes in the conductive patterns in a limited period of time. Two essentially identical so-called test and reference structures are placed close to each other on the same substrate and submitted to at least one sequence of a stress period and a measurement period. During a stress period, a DC current with a high current density is applied to the test structure thereby enhancing electromigration, while substantially simultaneous an AC current is applied to the reference structure leading to the same amount of power dissipation in said reference structure as the amount of power dissipation in said test structure, introduced by said DC stress current. The method of the present invention makes it possible to distinguish in a very accurate way between resistance changes induced by electromigration and resistance changes induced by other disturbances.
REFERENCES:
patent: 5264377 (1993-11-01), Chesire et al.
patent: 5497076 (1996-03-01), Kuo et al.
European Patent Office Search Report, Application No. EP 97 87 0149.
Scorzoni et al., "Electromigration in thin-film interconnection lines: models, methods and results", Materials Science Reports, 7, 142-220 (1991).
Patent Abstracts of Japan, vol. 15, No. 245 (P-1218), Jun. 24 1991 & JP 03 77080 A (Nippon Telegr. & Teleph. Corp.), Apr. 2 1991.
Ceuninck Ward De
De Schepper Luc
Goldoni Alessandro
Olmen Jan Van
Interuniversitair Micorelektronica Centrum (IMEC, vzw)
Nelms David
Wilson Christian D.
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