Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2007-01-30
2007-01-30
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Reexamination Certificate
active
10711536
ABSTRACT:
The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
REFERENCES:
patent: 5783465 (1998-07-01), Canning et al.
patent: 6908784 (2005-06-01), Farnworth et al.
Chen Paul
Ho Kai-Kuang
Hsuan Min-Chih
Liu Hermen
Wang Kun-Chih
Harrison Monica D.
Jianq Chyun IP Office
Jr. Carl Whitehead
United Microelectronics Corp.
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