Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-17
2001-08-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000
Reexamination Certificate
active
06281063
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing an isolation region and more particularly to a method for manufacturing a trench isolation in a semiconductor device.
2. Description of the Related Art
As the density of integrated circuits increases, the dimension of an isolation region between active regions in semiconductor devices decrease. With this trend, the conventional local oxidation of silicon (LOCOS) method for isolating active regions, which forms a field oxide layer by using a thermal oxidation technique, confronts the limit in the effective isolation length, thereby degrading characteristics of the isolation region. Furthermore, the conventional LOCOS method possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird's beak.
According to the disadvantages for LOCOS isolation structures mentioned above, an isolation technique using trenches has been developed. Generally, the trench isolation includes the steps of etching a silicon substrate to form a trench, depositing an oxide layer by using a chemical vapor deposition (CVD) process to fill up the trench, providing the oxide layer with a planarized surface using a chemical mechanical polish (CMP) process, and removing the oxide layer upon the active regions.
According to this technique, the semiconductor substrate is etched at a predetermined depth, thereby providing excellent characteristics of the device isolation. Furthermore, the field oxide layer is formed using a CVD technique, so that the device isolation region that is defined by a photolithography process can be maintained throughout.
However, the trench isolation technique described above has some drawbacks. For example, as shown in
FIG. 1
, a conventional trench isolation structure is illustrated. Residual polysilicon
104
a
,
104
b
are formed on the sharp corners of the interconnection between the trench isolation
102
and the surface of the silicon substrate
100
. The residual polysilicon
104
a
,
104
b
are usually formed in the deposition and etching processes of the polysilicon used as gate electrodes. They may conduct neighboring gate electrodes and cause various problems of short circuit. It is therefore desirable in the art to provide a method for manufacturing trench isolation structures without the problems mentioned above. It is towards those goals that the present invention is specifically directed.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to avoid the sharp corner of the interconnection between the diffusion layer and the conventional trench isolation structure. Alternatively, the invention prevents the residual polysilicon in the sharp corner formed in the etching process of the polysilicon used as gate electrodes in metal oxide semiconductor field effect transistors.
It is another object of this invention that the difficulty of the etching process of the polysilicon used as gate electrodes in metal oxide semiconductor field effect transistors can be reduced in spite of the shrinking of the design rule.
It is a further object of this invention that the problem of the short circuit of the gate electrodes, which is caused by the residual polysilicon in the sharp corners of the interconnections between the diffusion layers and the trench isolation, can be avoided.
To achieve these objects, and in accordance with the purpose of the invention, a silicon nitride layer used as an anti-diffusion layer mask that defines an isolation region on a silicon substrate and a thermal oxidation process that is performed on an active region are previously used before performing a conventional manufacturing process of a trench isolation. A silicon substrate having a first pad oxide layer and a first silicon nitride layer formed thereon is first provided. Then the first pad oxide layer and the first silicon nitride layer are patterned to form an anti-diffusion layer mask and to expose an active region of the silicon substrate. Next the silicon substrate is oxidized to form a first silicon dioxide layer, wherein lateral oxidation on the active region of the silicon substrate underneath the first pad oxide layer, the first silicon nitride layer provides an edge of the first silicon dioxide layer in the shape of a bird's beak. Moreover, the first silicon nitride layer, the first pad oxide layer and the first silicon dioxide are removed to expose the silicon substrate. Furthermore, a second pad oxide layer is formed on the substrate and a second silicon nitride layer is deposited thereon. Finally, an isolation trench of the invention can be formed by using a conventional method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5223736 (1993-06-01), Rodder
patent: 5468676 (1995-11-01), Madan
patent: 6033969 (2000-03-01), Yoo et al.
Jen Yi-Min
Pai Kuan-Te
Hoang Quoc
Nelms David
United Microelectronics Corp.
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