Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-27
2004-05-04
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S253000, C438S254000, C438S396000
Reexamination Certificate
active
06730956
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2002-27114 filed May 16, 2002, the contents of which are incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a method for manufacturing the storage node of a capacitor which is capable of increasing effective surface.
2. Description of the Related Art
As the integration of semiconductor devices such as dynamic random access memory (DRAM) devices increases, the fineness of patterns and a reduction of the design rule must be enforced. However, a reduction of the design rule creates difficulties in obtaining various semiconductor characteristics such as those of a transistor, cell capacitor, and wiring resistance.
Semiconductor devices require a certain cell capacitance depending on their particular characteristics. Typically, more than 30 pF capacitance per cell is required in a DRAM, taking into consideration the various coupling capacitance, leakage current, loss of electric charge due to an alpha particle during packing, and refreshing time. Accordingly, the reduction of the design rule has generated, numerous suggested methods for obtaining the required capacitance.
To obtain the required cell capacitance, two methods of using a dielectric layer, i.e., 1. using a dielectric constant which is relatively high, and 2. increasing the area of a capacitor, can be considered. However, it is widely known that these two methods present problems relating to the step coverage of a dielectric layer, leakage current, and reliability in using a new dielectric layer with a considerably high dielectric constant. As a result, studies on how to obtain sufficient capacitance to overcome the reduction of capacitance due to the reduction of the design rule have focused on methods for structurally securing the effective areas of a capacitor. One study relates to a method for increasing the effective surface area of a storage node by giving the storage node a three-dimensional shape, such as cylinder stack shape.
FIG. 1
is a schematic cross-sectional view illustrating a storage node
60
in the shape of a cylinder stack. Storage node
60
is electrically connected to a semiconductor substrate
10
between gate patterns
23
and
25
of the cell transistor formed on the active regions determined by an isolation region
15
. A gate oxide layer
21
can be interpositioned between the gate patterns
23
and
25
and the semiconductor substrate
10
. An electric connection is achieved by placing a conductive plug
35
through the insulating interlayer
40
and by placing a conductive pad
31
under the conductive plug
35
. Insulation between the conductive pad
31
and the gate patterns
23
and
25
is achieved by the capping layer
27
and spacer
29
.
As shown in
FIG. 1
, the cylindrical storage node
60
is connected to the lower conductive plug
35
. A mold layer (not shown in
FIG. 1
) is introduced to give the storage node
60
a cylindrical shape. The positioning of the storage node
60
is determined by patterning the mold layer. The storage node layer is then arranged with the patterns of the mold layer and is separated into individual storage nodes
60
by cells.
FIG. 2
is a schematic cross-sectional view illustrating the mold layer
70
which is introduced to form the storage node
60
into a cylindrical shape. Referring to
FIG. 2
, the mold layer
70
is formed to cover the insulating interlayer
40
and to have a thickness equivalent to the height of (i.e., co-planer to) the storage node
60
illustrated in
FIG. 1. A
supporter layer
50
may be introduced between the mold layer
70
and the insulating interlayer
40
. The supporter layer
50
supports the storage node
60
shown in
FIG. 1
, and further includes an etch stopper (not shown) for stopping the etching during the etch process for patterning the mold layer
70
.
The mold layer
70
is patterned by a photolithography process to have an opening
75
that exposes the lower conductive plug
35
. The region where the opening
75
is formed becomes the region where the storage node
60
is located. However, the region to be occupied by the storage node
60
may be formed in a slightly different shape from the region designed by the photo mask layout.
FIG. 3
is a schematic view illustrating the photo mask layout for opening
75
shown in FIG.
2
.
FIG. 4
is an illustration of the actual shape of the opening
75
.
FIG. 5
is an illustration of the shape of the storage node
60
that occupies the opening
75
. FIG.
6
is an illustration of the shape of a storage node
65
that is intended to be formed by the opening
75
.
The storage node region
71
has a substantially rectangular shape, as is shown in FIG.
3
. The storage node region
71
, designed to have a rectangular shape for the opening
75
, has a rectangular shape that extends in the direction of a bit line (not shown). After a photolithography process has been performed, the storage node region
71
has a substantially elliptical shape, such as the shape of the opening
75
shown in FIG.
4
. Thus, the photolithography process rounds the edge of the storage node region
71
on the mask layout. As a result, a cross-section of the storage node
60
of FIG.
1
and
FIG. 5
, which is deposited and separated along with the mold layer
70
of
FIG. 2
, does not have the designed rectangular shape. Instead, the cross-section of storage node
60
has a shape that is substantially elliptical.
The area occupied by the substantially elliptical storage node
60
or the area of the substantially elliptical opening
75
is less than the area of the designed (i.e., rectangular) for the storage node region
71
. Accordingly, the effective surface area of the storage node
60
is also less than that of the original design. Thus, the formed storage node
60
(i.e., elliptical shape) occupies an area less than that of the originally designed storage node
65
shown in
FIG. 6
(i.e., a rectangular shape).
To compensate for the loss of area, the process for forming the storage node
60
is performed so that the storage node
60
is extended to its maximum length along its axes. In particular, the length of the long axis is about 424 nm and the length of the short axis is about 75 nm. However, the extension of the storage node
60
may be limited by the lengths of the long axis, the short axis, and the cell pitch. To obtain more capacitance in a limited cell pitch, it is necessary to increase the height of the storage node
60
, but this is limited structurally by the photolithography process introduced to form the storage node
60
.
More specifically, if the height of the storage node
60
is increased, the probability of a hard fail, (e.g., a twin-bit fail,) increases due to the bridges between neighboring capacitors. If For example, if a storage node structure in the shape of a cylinder stack is used, electric shorts occurring between neighboring cell capacitors in a semiconductor device cause twin-bit fails.
The storage node in the shape of a cylinder stack presents a weak force for supporting the structure against external forces. Further, it is possible that bridges occur between the storage nodes if a sufficient distance between the storage nodes is not obtained due to items such as changes in the stress of the lower layers supporting the storage node or changes in the node itself. Accordingly, bridges formed between storage nodes may prevent an increase in the effective surfaces of a capacitor.
SUMMARY OF THE INVENTION
At least one exemplary embodiment of the present invention provides a method for manufacturing the storage node of the capacitor of a semiconductor device which can reduce the occurrence of pattern bridges between the storage nodes of a cell capacitor and in increasing the capacitance of the capacitor.
At least one exemplary embodiment of the present invention provides a meth
Bae Dong-il
Lee Sang-hyeon
Shin Dong-won
Harness Dickey
Quach T. N.
Samsung Electronics Co,. Ltd.
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