Method for manufacturing surface channel type P-channel MOS tran

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438532, 438923, H01L 21336

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active

061598097

ABSTRACT:
In a method for manufacturing a surface channel type P-channel MOS transistor, a gate insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating layer. Then, a P-type impurity diffusion preventing operation is performed upon the gate electrode, and P-type impurities are implanted into the gate electrode.

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Y.H. Lin, C.S. Lai, C.L. Lee, T.F. Lei, T.S. Chao. Nitridization of the Stacked Poly-Si Gate to Suppress the Boron Penetration in pMOS. IEEE Electron Device Letters, Vo. 16 No. 6, Jun. 1995. P. 248-249.
W.T. Sun, S.H. Chen, C.J. Lin, T.S. Chao, C.C.-H Hsu. Process Optimization for Preventing Boron-Penetration Using P or As Co-Implant in P-Poly Gate of P-MOSFETs. 1995 International Symposium on VLSI Technology, Systems, and Applications. Jun. 1995 P. 40-43.
Second Office Action of Japanese Application No. 8-167284 Issued on Oct. 6, 1998.
European Patent Office; Patent Abstracts of Japan; Publication Number: 02078229; Publication Date: Mar. 19, 1990; Title: Field-Effect Transistor and it's Manufacture.
Extended Abstracts of the 1995 International Conference; Title: Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter Micron LDD MOSFETs; Author: Shimizu et al.; Date: Aug. 21, 1995.
European Search Report; Date: Mar. 27, 1998.

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