Method for manufacturing semiconductor memory devices

Details Method for manufacturing semiconductor memory devices Method for manufacturing semiconductor memory devices

2000-09-11

2002-08-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S225000, C438S396000, C438S398000

Reexamination Certificate

active

06436761

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for manufacturing semiconductor memory devices and, more particularly, to a method for manufacturing semiconductor memory devices which each store therein information utilizing a capacitive element having an HSG (Hemispherical Grain) structure.
2. Description of the Related Art
Semiconductor memory devices (memories) are roughly classified into DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories), most of which are comprised of MOS (Metal Oxide Semiconductor) transistors excellent in integration density. Further, a DRAM can enjoy the above-mentioned advantage of high integration density more than an SRAM, to lower costs, thus finding a wide application field of various memory apparatuses including information equipment.
Also, since the DRAM utilizes capacitive elements to store information based on existence
onexistence of charge in each of capacitive elements, it is necessary to limit a resultantly large area due to increasing integration density which area is occupied by these capacitive elements on its semiconductor substrate; with this, to compensate for a resultant decrease in capacitance of each capacitive element, various techniques have been worked out in terms of structure of the capacitive elements.
With this, the DRAM includes a switching transistor (memory-cell selecting transistor) consisting of the above-mentioned MOS transistor for controlling inputting/outputting of information to its capacitive elements, in such a configuration that that memory-cell selecting transistor and one such capacitive element may make up a one-bit memory cell. Each capacitive element is connected to either a source of a drain of the MOS transistor of each memory-cell selecting transistor, so that information read/write operations are performed to the capacitive element when a word-line signal is applied to a gate electrode of that MOS transistor to turn it ON or OFF.
Since the capacitive elements are reduced in size with improvements in integration density and fine patterning of DRAMs, an appropriate method must be developed to increase the capacitance of each of the capacitive elements. In an attempt to do so, one method is provided for increasing surface area of capacitive insulator film of each capacitive element. Another method is provided for reducing film thickness of the capacitive insulator film. Conventionally, the above-mentioned HSG technology has been employed. This HSG technology attempts to form an HSG on a surface of a lower electrode of each capacitive element, to thereby increase the surface area of the capacitive insulator film.
As shown in
FIG. 14
, for example, on a P-type silicon substrate
51
of a DRAM, N-type source region
52
and N-type drain region
53
, a gate insulator film
54
, and a gate electrode
55
are formed in a region isolated by an element-isolating insulator film
57
, thus forming an N-type MOS transistor
56
as the memory-cell selecting transistor. The gate electrode
55
here is connected to a word line and a source electrode (not shown), to a bit line. Also, so as to cover a whole surface, a first inter-layer insulator film
58
and a second inter-layer insulator film
62
are formed, in such a configuration that the first inter-layer insulator film
58
has a first contact hole
59
formed therein, in which first contact hole
59
is so formed a contact plug
60
as to be connected to the N-type drain region
53
and also the second inter-layer insulator film
62
has a second contact hole
63
formed therein, in which second contact hole
63
is so formed a capacitive element
70
as to be connected to the contact plug
60
.
Thus, the capacitive element
70
is provided with a lower electrode
71
, a capacitive insulator film
72
, and an upper electrode
73
. The lower electrode
71
has an HSG
74
formed by HSG technology thereon. Also, the lower electrode
71
has an impurity diffused therein to prevent lowering of its capacitance due to its own depletion and has a barrier film
75
formed thereon to prevent the impurity from being diffused to outside.
With this, after the capacitive insulator film
72
is formed on the barrier film
75
, this capacitive element
70
needs to undergo oxidation processing (annealing) to suppress a leakage current and an initial failure rate caused by being a capacitive element. Conventionally, this oxidation has been performed using an FA (Furnace Anneal) processing at about 800° C. which uses a diffusion furnace as its heating source.
Recently, on the other hand, with progress in the semiconductor processing technologies, a semiconductor device,such as a processor and a like, having a large-scale logic part and DRAM part mixed on a same semiconductor substrate has been developed. To improve the operation speed of such the semiconductor device, such a device region as constituting the logic part, in particular, needs to undergo a suicide process, so that the above-mentioned device requires for its manufacturing a lowered processing temperature, that is, so-called low-temperature processes.
The prior-art method for manufacturing the semiconductor device, however, suffers from the following problems.
A first problem is that although the capacitive element can be increased in capacitance by employing the HSG technology, its service life is degraded as compared to those manufactured without using the HSG technology. The reasons for this problem are described below with reference to
FIGS. 12A and 12B
.
As shown in
FIG. 12A
, when the lower electrode
71
has an HSG
71
a
formed thereon, this HSG
71
a
in turn has a sharp constriction
71
b
formed at its root. This remarkably damages coverage of the capacitive insulator film
72
formed above the lower electrode
71
, thus reducing a film thickness T of a part of the capacitive insulator film
72
as shown enlarged in
FIG. 12B
which part is formed near that constriction
71
b
and its vicinity portion A. Therefore, an electric field is concentrated during operation to the above-mentioned part of the capacitive insulator film
72
having a small film thickness T at the constriction
71
b
, to cause a leakage current to flow from that portion, thus degrading the service life of the capacitive element. Specifically, its service life is shortened by roughly one digit as compared to a capacitive element having no HSG formed thereon. With this, it needs to be improved so as to enjoy a service life almost equivalent to that of the capacitive element having no HSG formed thereon.
A second problem is that when the capacitive insulator film is decreased in film thickness to increase the capacitance of the capacitive element, larger thermal stress is applied which is generated by oxidation performed after that capacitive insulator film is formed, thus increasing occurrence of initial failure rates.
That is, as mentioned above, after the capacitive insulator film is formed, for example to reduce the leakage current and-the initial failure rate due to being a capacitive element, oxidation is required by use of, for example, the above-mentioned FA processing, in which case, however, influence of the thermal stress applied during this oxidation process cannot be avoided if processing temperature is high. To reduces this influence, the oxidation process must be performed at a lower temperature, but if the temperature is lowered too much, an essential object cannot achieved by the oxidation process. Therefore, the thermal stress must be suppressed to thereby reduce the initial failure rate.
FIG. 13
is plotted in terms of a TDDB (Time Dependent Dielectric Breakdown) property. As can be seen from the
FIG.13
, formation of the HSG degrades the service life and the reduction in a film thickness Teff (film thickness, calculated as oxide film thickness) of the capacitive insulator film further degrades the capacitive element.
A third problem is that processing for preventing depletion of a capacitive element, which is required by a temperature-lowering p

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