Method for manufacturing semiconductor memory device

Details Method for manufacturing semiconductor memory device Method for manufacturing semiconductor memory device

1999-12-14

2001-07-10

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S239000

Reexamination Certificate

active

06258650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high degree of integration of a semiconductor memory device and, more specifically, to a semiconductor memory device including memory cells formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
In a semiconductor integrated circuit, especially, a semiconductor memory device such as a DRAM, the area of memory cells has recently been decreased more and more in accordance with a remarkably high degree of integration. This necessitates miniaturizing charge storage layers constituting the memory cells, transistors, and element isolation regions each formed between the memory cells, thus causing various problems. For example, if the area of the charge storage layers is reduced, a sufficient amount of charge cannot be stored, the transistors are difficult to control, and an isolation withstand voltage cannot be obtained sufficiently between the memory cells.
Various methods for resolving the above problems have been considered and put to practical use. For instance, the area of the charge storage layers can be secured by forming the layers above both the transistors and bit lines. If the memory cells are formed on an island-like semiconductor substrate insulatively formed in an insulation film, the isolation withstand voltage can be enhanced, and the short channel effect can be suppressed, thereby improving in controllability of the transistors.
A conventional stacked capacitor type memory cell adopting the above method has, for example, the following structure. An insulation layer is formed on a semiconductor substrate, and a monocrystalline silicon layer is formed on the insulation layer. To form the monocrystalline silicon layer on the insulation layer is called the SOI structure. The monocrystalline silicon layer is surrounded with an element isolation region reaching the insulation layer thereby to form an element region. The element region is isolated like an island, and a gate insulation film is selectively formed in the isolated element region. A gate electrode is formed on the gate insulation film, and two diffusion layers (source and drain regions) are formed on the surface of the element region so as to interpose the gate electrode therebetween. These gate insulation film, gate electrode and diffusion layers constitute a transistor. One of the source and drain regions of the transistor is connected to a bit line formed above the gate electrode. The other one of the source and drain regions is connected to a storage electrode formed thereon. The storage electrode is opposite to a plate electrode formed higher than the bit line, thus constituting a capacitor (see FIG.
15
).
In the conventional memory cell, signal data transmitted through the bit line is stored in the storage electrode through the transistor, and the data stored in the electrode is read out and supplied to the bit line through the transistor.
As described above, in the conventional memory cell, since a transistor is formed on the semiconductor substrate isolated in the insulation film, the short channel effect can be suppressed and the element isolation withstand voltage can be increased. Since, furthermore, a capacitor can be formed on the gate electrode and the bit line, the area for the capacitor can be secured. Consequently, various problems due to miniaturization of memory cells can be resolved.
However, in the conventional memory cell, the storage electrode is formed so as to cover the bit line with the insulation film interposed therebetween, a very deep connecting hole has to be opened in order to connect the storage electrode to one of the source and drain regions. The miniaturization of memory cells makes it very difficult to prevent the storage electrode from being short-circuited with the gate electrode and the bit line, and the connecting hole is required to be very correctly self-aligned with the gate electrode and the bit line.
Conventionally, it is considerably difficult to manufacture a memory cell having an area enough to form a capacitor and having a transistor improved in element isolation withstand voltage and in controllability, without causing the storage electrode to be short-circuited with the gate electrode and the bit line.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a semiconductor memory device in which a large area for forming a capacitor is secured, a transistor is excellent in element isolation withstand voltage and controllability, a storage electrode can be prevented from being short-circuited with a gate electrode and a bit line.
A second object of the present invention is to provide a method for manufacturing a semiconductor device having the above constitution.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising:
a substrate;
a first insulation layer formed on the substrate;
a plurality of bit lines arranged in one direction on the first insulation layer and separated from one another;
a second insulation layer formed all over the plurality of bit lines and having a plurality of openings;
a plurality of via conductive layers buried into at least the plurality of openings;
an element isolating region formed on the second insulation layer;
a plurality of island-like element forming semiconductor regions formed as surrounded by the element isolating region;
a plurality of transistors formed in the plurality of island-like element forming semiconductor regions, each of the plurality of transistors including:
a gate electrode insulatively formed on a corresponding one of the plurality of island-like element forming semiconductor regions, the gate electrode extending in a direction crossing the plurality of bit lines and serving as a word line;
a first and a second diffusion region formed on both sides of the gate electrode in a direction crossing the word line and formed on the one of the plurality of island-like element forming semiconductor regions, the first diffusion region being connected to a corresponding one of the plurality of bit lines through a corresponding one of the plurality of via conductive layers; and
a plurality of capacitors corresponding to the plurality of transistors, each of the plurality of capacitors including:
a storage electrode formed on the second diffusion region, the storage electrode being electrically connected to the second diffusion region;
a capacitor insulation film formed on the storage electrode; and
a plate electrode formed on the capacitor insulation film, the plate electrode being connected in common to the plurality of capacitors.
It is preferable that the bit lines be formed of tungsten.
The bit lines can also be formed of monocrystalline silicon, and the island-like element forming semiconductor regions and via conductive layers can be formed integrally with the bit lines as a monocrystalline layer and, in this case, the monocrystalline layer needs to be doped.
In the semiconductor memory device according to the first aspect of the present invention, since the bit lines are formed under the semiconductor layer, in which the MOS transistor is formed, with the insulation layer therebetween, it is less possible that a short circuit will occur between the bit lines and storage electrode than in the prior art structure wherein the bit lines are interposed between the storage electrode and semiconductor layer. Since the semiconductor layer is isolated like an island on the insulation layer, both transistor controllability and element isolation withstand voltage can be improved. Since, furthermore, the capacitor including the storage and plate electrodes is formed on the top of the structure, sufficient charges can be stored by effectively utilizing the area of the memory cell, with the result that the semiconductor memory device can be improved in performance.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
a substrate;
an insulati

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