Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-28
2001-10-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S682000, C438S683000, C438S587000, C438S588000
Reexamination Certificate
active
06300194
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method for manufacturing electronic memory devices integrated in a semiconductor having a virtual ground cells matrix.
BACKGROUND OF THE INVENTION
EPROM and Flash EPROM electronic memory devices integrated in a semiconductor include a number of non-volatile memory cells organized into a matrix; that is, the cells are arranged into rows, or word lines, and columns, or bit lines. Each non-volatile memory cell includes a MOS transistor with a floating gate electrode located above the channel region, i.e., shows a high d.c. impedance to all the other terminals of a cell and to the circuit in which the cell is incorporated.
The cell also includes a second electrode, known as the control gate, which is driven by suitable control voltages. The other electrodes of the transistor are conventional drain, source, and body terminals.
In recent years, considerable effort has been made to provide memory devices of higher circuit density. This has resulted in the development of electrically programmable non-volatile memory matrices of the contactless type, having a so-called “tablecloth” or crosspoint structure. One example of a matrix of this kind, and its fabrication process, is described in European Patent No. 0 573 728 to this Applicant, and is herein incorporated by reference.
In this class of matrices, the memory cells have source/drain regions formed in the substrate by continuous parallel diffusion strips, known as the bit lines, which are substantially coincident with the matrix columns.
A contactless matrix requires virtual ground circuitry for the reading and programming operations. However, the savings in circuit area afforded by such a structure is remarkable, allowing approximately of one order of magnitude higher number of contacts to be provided.
In this type of virtual ground matrix, parallel strips are defined of a which include a layer of gate oxide, a first layer of polysilicon, an interpoly dielectric layer, and a capping polysilicon layer known as the Poly Cap. These strips form the gate electrodes of the memory cells.
In openings between the various gate electrodes, an implantation, e.g., of arsenic where the substrate is of the P type, is performed to provide the source and drain region diffusion (bit lines).
At this stage of the process the gate electrodes, which are located between previously exposed bit lines, are sealed to permit the implanting steps. An oxidation step allows the dopant to diffuse under the gate electrodes.
This technique causes an increased resistance of the bit lines as the cell size decreases, particularly to less than 0.4-0.5 &mgr;m. The resistance of implanted regions, such as the bit lines, is inversely proportional to the square of the width of those regions.
In addition, where the cell size is made exceedingly small, the length of the channel region becomes quite difficult to control. The actual length of the channel region of a MOS transistor is known to depend on: the size of the gate electrode, itself dependent on photolithography and etching operations on the polysilicon layers; implantations in the channel region controlling the cell performance in terms of threshold voltage and current; and the lateral diffusion of the implanted source/drain regions due by the thermal treatments to which the semiconductor is subjected after the implantation step.
SUMMARY OF THE INVENTION
Embodiments of the invention provide an improved process for manufacturing electronic memory devices integrated in a semiconductor having a virtual ground cells matrix, whereby the memory cells exhibit fairly low surface resistances and a longer channel than in prior art devices.
Therefore, embodiments of the invention provide memory cells of a reduced size whose implanted regions, such as the bit lines of the virtual ground memory cells, are salicided and formed by implantation at a low dopant concentration, thereby affording improved control of the cell channel region length.
Presented is a process for manufacturing virtual ground electronic memory devices integrated in a semiconductor of a first type and having at least one matrix of floating gate memory cells. In the matrix there are a number of continuous bit lines extending across the substrate as discrete parallel strips, and a number of word lines extending in a transverse direction to the bit lines. The method begins by forming gate regions of the memory cells to produce a number of continuous strips separated by parallel openings. Then, a dopant is implanted to form, within the parallel openings, the bit lines with conductivity of a second type. Spacers are formed on sidewalls of the gate regions. Then a first layer of a transition metal is deposited into the parallel openings, and the transition metal layer is subjected to a thermal treatment for reacting it with the semiconductor substrate and forming a silicide layer over the bit lines.
The features and advantages of a method according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5087584 (1992-02-01), Wada et al.
patent: 5340768 (1994-08-01), Gill
patent: 5470772 (1995-11-01), Woo
patent: 5683941 (1997-11-01), Kao et al.
patent: 0 386 631 A2 (1990-09-01), None
patent: 0 811 983 A1 (1997-12-01), None
patent: WO 96/08840 (1996-03-01), None
Besana Luca
Locati Vanda
Noris Chiorda Gianluigi
Elms Richard
Galanthay Theodore E.
Iannucci Robert
Owens Beth E.
Seed IP Law Group PLLC
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