Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-09
2002-04-23
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S296000
Reexamination Certificate
active
06376316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device including a plurality of kinds of field effect transistors having gate insulating films of different thicknesses.
BACKGROUND OF THE INVENTION
One of the techniques supporting the high integration of a semiconductor memory is known as element isolation. The element isolation of a semiconductor integrated circuit device using the 0.25-microns technique, such as a random access memory (hereinafter abbreviated to the DRAM) of 64 Mbits, has been developed from the LOCOS (Local Oxidation of Silicon) element isolation of the prior art to the so-called groove type element isolation, in which element forming regions are insulated and isolated by forming grooves in the element isolating regions of a silicon substrate and by forming a buried insulating film in the grooves. This groove type element isolation enables an element isolation length of 0.3 microns or less, which has been impossible to achieve by LOCOS element isolation, thereby to improve the degree of memory isolation greatly.
Meanwhile, in addition to the market needs for a lower voltage and small power consumption, the rapid spread of portable devices, such as the PDAs (Personal Digital Assistants) and electronic still cameras has intensified the demand for the simultaneous on-chip location of the elements which have been formed in different chips in the prior art. For example, microcomputers have been manufactured having a built-in flash memory or microcomputers having a built-in DRAM of an intermediate capacity have been manufactured.
SUMMARY OF THE INVENTION
On these semiconductor integrated circuit devices having devices of different functions, there are mounted a plurality of kinds of field effect transistors having different operating voltages. For the operations to write/erase information in/from the flash memory, for example, a voltage as high as 15 to 20 [V] is required, so that in part of the peripheral circuits, field effect transistors having a gate insulating film with a thickness of 15 to 25 [nm] capable of withstanding such a voltage application are used. In the logic circuit section of the microcomputer operating at an ordinary voltage of 3.3 [V], there are used field effect transistors having a gate insulating film with a thickness of 7 to 10 [nm]. In order to realize high-speed operation at a supply voltage as low as about 1.8 [V] in a microcomputer with a built-in flash memory according to the 0.25 micron technique of recent years, there are used in the logic circuit section, field effect transistors which have a gate insulating film with a thickness of 4 to 5 [nm]. In order that the input/output units may operate also at 3.3 [V], it is necessary to form gate insulating films of three types: a gate insulating film having a thickness of 4 to 5 [nm] (for 1.8 [V]); a gate insulating film having a thickness of 7 to 10 [nm] (for 3.3 [V]); and a gate insulating film having a thickness of 15 to 25 [nm] (for a flash memory). In short, it is necessary to form gate insulating films having three different thicknesses.
We have discovered the following problem by investigating the technique used when two kinds of gate insulating films having different thicknesses are separately formed over two elements forming regions of the silicon substrate, insulated and isolated by the aforementioned groove type element isolation. This problem will be described with reference to FIGS.
40
(A) to
46
. Of FIGS.
40
(A) to
46
, FIGS.
40
(A) to
44
are sections for explaining the problem, FIGS.
40
(A) to
42
are sections (corresponding to a later-described
FIG. 2
) of a field effect transistor, taken in the gate length direction, and
FIGS. 43 and 44
are sections (corresponding a later description referring to
FIG. 3
) of a field effect transistor, taken in the gate width direction.
FIG. 45
is a diagram for comparing the breakdown voltage distribution (a) of a capacitor with the groove type element isolation and the breakdown voltage distribution (b) of a capacitor with the LOCOS element isolation.
FIG. 46
is a diagram for comparing the sub-thresh characteristics (a) of a field effect transistor with the groove type element isolation and sub-thresh characteristics (b) of a field effect transistor with the LOCOS element isolation. In
FIG. 45
, the abscissa indicates a capacitor gate applied voltage, and the ordinate indicates the cumulative number of defects. In
FIG. 46
, the abscissa indicates the gate voltage, and the ordinate indicates the drain current.
First, as shown in FIG.
40
(A), the groove type element isolation is achieved by forming grooves
152
for defining a first element forming region and a second element forming region in element isolating regions of a main surface of a silicon substrate
151
, and subsequently by forming a buried insulating film
153
of a silicon oxide film in the grooves
152
. After this, an impurity introducing buffer insulating film
154
is formed over the first element forming region and the second element forming region. After this, channel implantation layers
155
A and
155
B for controlling the threshold voltages of the field effect transistors are individually formed in the individual surface layers of the first element forming region and the second element forming region.
Next, the buffer insulating film
154
is removed, and thermal oxidation is then executed to form a gate insulating film
156
made of a thermally oxidized (SiO
2
) film having a thickness of about 20 [nm], over the first element forming region and the second element forming region, as shown in FIG.
40
(B).
Next, a mask
157
is formed by using the photolithographic technique so as to cover the first element forming region, while leaving the second element forming region open.
Next, the mask
157
is used as an etching mask to remove the gate insulating film
156
from over the second element forming region by a wet-etching method using an aqueous solution of hydrofluoric acid, as shown in FIG.
41
(C).
Next, the mask
157
is removed, and thermal oxidation is executed to form a gate insulating film
158
of a thermally oxidized (SiO
2
) film having a thickness of about 5 [nm], over the second element forming region, as shown in FIG.
41
(D). At this step, the gate insulating film
156
and the gate insulating film
158
of different thicknesses can be separately formed over the first element forming region and the second element forming region which are insulated and isolated by the groove type element isolation.
Next, gate electrodes
159
of a polycrystalline silicon film doped with an impurity are individually formed over the first element forming region and the second element forming region. After this, a pair of semiconductor regions
160
for the source region and the drain region are formed in the surface layer of the first element forming region. After this, a pair of semiconductor regions for the source region and the drain region are formed in the surface layer of the second element forming region. Thus, there are formed a field effect transistor Q
12
and a field effect transistor Q
13
having gate insulating films of different thicknesses, as shown in FIG.
42
. Here, the individual gate electrodes of the field effect transistors Q
12
and Q
13
are so formed that their the gate electrodes in the gate width direction are led out over the buried insulating film
153
, as shown in
FIGS. 43 and 44
.
In the separate formation of the gate insulating films by the technique of the prior art, when the gate insulating film
156
is removed from the second element forming region by a wet-etching method, the buried insulating film
153
buried in the grooves
152
is simultaneously etched off, as shown in FIG.
41
(C). As a result, a step exposing the s
Shukuri Shoji
Suzuki Norio
Taniguchi Yasuhiro
Antonelli Terry Stout & Kraus LLP
Chaudhuri Olik
Hitachi , Ltd.
Pham Hoai
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