Method for manufacturing semiconductor integrated circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S279000

Reexamination Certificate

active

07417291

ABSTRACT:
Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

REFERENCES:
patent: 5545578 (1996-08-01), Park et al.
patent: 5796151 (1998-08-01), Hsu et al.
patent: 6417084 (2002-07-01), Singh
patent: 6448140 (2002-09-01), Liaw
patent: 6458646 (2002-10-01), Divakaruni
patent: 6566236 (2003-05-01), Syau et al.
patent: 11-261059 (1999-09-01), None
patent: 2000-136072 (2000-05-01), None
A fully Working 0.14 μm Dram Technology With Polymetal Gate, Jung et al IEDM 2000 pp. 365-368.

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