Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-16
2004-02-24
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S637000, C438S656000, C438S688000
Reexamination Certificate
active
06696357
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. Particularly, the present invention is concerned with a technique which is effectively applicable to the improvement of adhesion between a bonding pad and an interlayer insulating film which underlies the bonding pad.
In Japanese Published Unexamined Patent Application No. Hei 5(1993)-160133 there is disclosed a technique in which a through hole extending up a bonding pad is formed in a surface protecting film formed on the whole surface of a semiconductor substrate, then W (tungsten) film is formed in the interior of the through hole, and thereafter an Al (aluminum) electrode is formed on the W film and surface protecting film, thereby making the area of opening of the through hole smaller than the diameter of a bonding wire.
In Japanese Published Unexamined Patent Application No. 2001-185552 there is disclosed a technique in which plural plugs integral with a bonding pad are formed on an interlayer insulating film just underlying the bonding pad, thereby improving the adhesion between the bonding pad and the interlayer insulating film to prevent the peeling of the bonding pad.
SUMMARY OF THE INVENTION
Recently, with high integration of LSI and consequent decrease of chip size, there has been a tendency toward a decrease in the size of bonding pads.
The present inventors have found out that a peeling phenomenon at the interface between a top Al (aluminum) wiring layer constituting a bonding pad and an underlying interlayer insulating film is being actualized due to an increase of stress applied to the bonding pad under vibration and loading in wire bonding. Particularly, in a MCP (Multi-Chip Package) manufacturing process, there is used a KGD (Known Good Die) technique for guaranteeing the quality of individual chips before assembly. In this case, wires are bonded onto bonding pads at the time of the individual chip inspection and also at the time of the package inspection stage, so that the peeling of bonding pads is more likely to occur.
Forming the bonding pads by a two-layer structure of a top Al wiring layer and an underlying Al wiring layer to enhance the strength thereof may be an effective means for preventing the peeling of the bonding pads. In this case, however, an interlayer insulating film formed of silicon higher in hardness than Al is interposed between the two Al wiring layers, so that the interlayer insulating film may be cracked by impact in wire bonding and this crack may cause peeling of the bonding pads.
It is an object of the present invention to provide a technique which can prevent the peeling of a bonding pad.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
Typical inventions disclosed herein will be outlined below.
In a first aspect of the present invention there is provided a semiconductor integrated circuit device comprising:
(a) a first conductor piece disposed on a first insulating film formed on a semiconductor substrate;
(b) a second insulating film disposed on the first insulating film and the first conductor piece and having a first aperture on the first conductor piece;
(c) a second conductor piece formed in the interior of the first aperture and having a film thickness smaller than the depth of the first aperture at a central plane portion of the first aperture, the second conductor piece being electrically connected to the first conductor piece; and
(d) a third conductor piece disposed on the second conductor piece and being in contact with the second conductor piece.
In a second aspect of the present invention there is provided, in combination with the first aspect, a semiconductor integrated circuit device wherein the second conductor piece includes a tungsten layer.
In a third aspect of the present invention there is provided, in combination with the second aspect, a semiconductor integrated circuit device wherein the third conductor piece includes an aluminum layer.
In a fourth aspect of the present invention there is provided, in combination with the third aspect, a semiconductor integrated circuit device including a third insulating film, the third insulating film being disposed on the second insulating film and the third conductor piece and having a second opening in an area to which a wire is connected.
In a fifth aspect of the present invention there is provided a semiconductor integrated circuit device comprising a semiconductor substrate having on a main surface thereof a first area and a second area different from the first area; a first insulating film formed on the main surface of the semiconductor substrate; a first conductor piece disposed on the first insulating film in the first area; a fourth conductor piece disposed on the first insulating film in the second area; a second insulating film disposed on the first insulating film and the first and fourth conductor pieces and having a first aperture on the first conductor piece and also having a third aperture on the fourth conductor piece; a second conductor piece formed in the interior of the first aperture and having a film thickness smaller than the depth of the first aperture at a central plane portion of the first aperture, the second conductor piece being electrically connected to the first conductor piece; a fifth conductor piece formed in the interior of the third aperture and having a film thickness almost equal to the depth of the first aperture at a central plane portion of the first aperture, the fifth conductor piece being electrically connected to the fourth conductor piece; a third conductor piece disposed on the second conductor piece in the first area and being in contact with the second conductor piece; a sixth conductor piece disposed on the fifth conductor piece in the second area and being in contact with the fifth conductor piece; a third insulating film disposed on the second insulating film and the third and sixth conductor pieces and having a second aperture to which a part of the third conductor piece is exposed; and a wire connected to the third conductor piece within the second aperture.
In a sixth aspect of the present invention there is provided, in combination with the fifth aspect, a semiconductor integrated circuit device wherein the second and fifth conductor pieces include a tungsten layer.
In a seventh aspect of the present invention there is provided, in combination with the sixth aspect, a semiconductor integrated circuit device wherein the third and sixth conductor pieces include an aluminum layer.
In an eighth aspect of the present invention there is provided, in combination with the fifth aspect, a semiconductor integrated circuit device wherein the third insulating film includes a silicon nitride film.
In a ninth aspect of the present invention there is provided, in combination with the fifth aspect, a semiconductor integrated circuit device wherein the second and fifth conductor pieces include a laminate structure of a titanium layer, a titanium nitride layer and a tungsten layer.
In a tenth aspect of the present invention there is provided, in combination with the fifth aspect, a semiconductor integrated circuit device wherein the diameter in a plane pattern of the third aperture is smaller than the diameter in a plane pattern of the first aperture.
In an eleventh aspect of the present invention there is provided, in combination with the fifth aspect, a semiconductor integrated circuit device wherein the first insulating film includes an insulating film having a dielectric constant of 4 or less.
In a further aspect of the present invention there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of forming a first insulating film on a semiconductor substrate; forming a first conductor piece on the first insulating film; forming a second insulating film on the first insulating film and the first conductor piece and thereafter forming a
Ashihara Hiroshi
Fujiwara Tsuyoshi
Imai Toshinori
Shiraishi Tomohiro
Yoshida Masaaki
Jr. Carl Whitehead
Miles & Stockbridge P.C.
Renesas Technology Corporation
Smoot Stephen W.
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