Method for manufacturing semiconductor devices

Details Method for manufacturing semiconductor devices Method for manufacturing semiconductor devices

2001-04-17

2003-08-05

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S528000, C438S981000

Reexamination Certificate

active

06602751

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for manufacturing semiconductor devices and, more particularly to, a method for manufacturing semiconductor devices in each of which three kinds of MOS (Metal oxide Semiconductor) transistors having a gate oxide film with different film thicknesses respectively are formed.
The present application claims priority of Japanese Patent Application No. 2000-115695 filed on Apr. 17, 2003, which is hereby incorporated by reference.
2. Description of the Related Art
Most LSIs (Large Scale Integrations), known as a representative of semiconductor devices, are made up of MOS transistors and are excellent for integration density. Such a MOSLSI can utilize its high integration density to reduce costs, thus finding wide applications in a variety of electronic equipment.
In a field of those LSIs, recently, such a type of LSI has been developed called a SOC (System On Chip) that incorporates on its one semiconductor chip a plurality of memories and logics to have desired functions. Since this type of LSI is typically incorporated and used in portable electronic equipment, it is designed to operate on a battery power source and also at the lowest possible source voltage for reducing power consumption.
The logics required in the above-mentioned type of LSI to provide desired functions are made up of a combination of MOS transistors having different properties, specifically of a plurality of kinds of MOS transistors having a gate oxide film with different film thicknesses respectively. The properties of the MOS transistors mainly depend or the film thickness of the gate oxide film in that a thinner the film thickness, a larger becomes an ON-state current, thus enabling high-speed operations. If the gate oxide film is thin, however, a gate leakage current increases, thus running counter to the purpose of power saving. Accordingly, to save power, it is necessary nor to form the gate oxide film too thick.
FIG. 8
schematically illustrates an example of an important portion, of a semiconductor device, that includes a logic circuit made up of three kinds of MOS transistors having different film thicknesses of the gate oxide film. As shown in
FIG. 8
, this semiconductor device
100
includes a core transistor (high-speed operational transistor)
101
made up of a first kind of MOS transistor M
1
(
FIG. 7
) having a small film thickness for high speed operations of arithmetic/logical operations, image processing, or a like, a sub-core transistor (power saving transistor)
102
consisting of a second kind of MOS transistor M
2
(
FIG. 7
) having a medium film thickness for arithmetic/logical operations, image processing, or a like which do not require such high speed operations as those of the core transistor
101
, and a peripheral transistor (low-speed operational transistor
103
consisting of a third kind of MOS transistor M
3
(
FIG. 7
) having a large film thickness which needs not operate at a high speed for driving peripheral circuitry including I/O (input/output) circuits or a like.
Here, terms of small film thickness, medium film thickness, and large film thickness of the gate oxide film do not refer to absolute small, mediums and large values of the gate oxide film thickness respectively but refer to a relative comparison in film thickness of the three kinds of MOS transistors having different gate oxide film thicknesses.
FIG. 7
is schematic cross-sectional view of a specific construction of the semi conductor device
100
as shown in FIG.
8
. As shown in
FIG. 7
, on a same semiconductor substrate
111
of the semiconductor device
100
are formed the first kind of MOS transistor M
1
which makes up the core transistor
101
and has a small gate oxide films thickness of 1.5-2.0 nm, the second kind of MOS transistor M
2
which makes up the sub-core transistor
102
and has a medium gate oxide film thickness of 2.2-2.5 nm, and the third kind of MOS transistor M
3
which makes up the peripheral transistor
103
and has a large gate oxide film thickness of 3.5-7.5 nm.
The first through third kinds of MOS transistors M
1
through M
3
have source regions
66
through
68
, drain regions
7
through
73
, three different thicknesses of gate oxide films, a small-thickness gate oxide film
61
, a medium-thickness gate oxide film
62
, and a large-thickness gate oxide film
52
, gate electrodes
63
through
65
, and gate side walls
74
through
76
respectively. Each of the source regions
66
through
68
and each of the drain regions
71
through
73
may be either of a so-called “LDD (Lightly Doped Drain) construction” consisting essentially of a high impurity concentration region and a low impurity concentration region or a so-called “non-LDD construction” consisting essentially of only a high impurity concentration region.
Of these three kinds of MOS transistors M
1
through M
3
, the second kind of MOS transistor M
2
making up the sub-core transistor
102
is provided to meet the purpose of power saving with a not so high operation speed as that of the core transistor
101
, in such a configuration that its gate oxide film is formed thicker than the first kind of MOS transistor M
1
but thinner than the third kind of MOS transistor M
3
making up the peripheral transistor
103
.
Accordingly, by forming the second kind of MOS transistor M
2
to provide the sub-core transistor
102
, such an above-mentioned multifarious-functional LSI can be manufactured that can operate at a moderately high speed in arithmetic/logical operations, image processing, and a like with saved power dissipation.
The following will describe a prior art method for manufacturing a semiconductor device along its steps with respect to FIG.
6
A through FIG.
6
K.
First, as shown in
FIG. 6A
, for example, a P-type silicon substrate
51
is oxidized to form throughout thereon a first gate oxide film
52
a
to a thickness of 3-7 nm as an initial gate oxide film. As described later, the first gate oxide film
52
a
provides the large-thickness gate oxide film
52
of the third kind of MOS transistor M
3
making up the peripheral transistor
103
. Next, as shown in
FIG. 6B
, a photo-resist film
53
is applied on a whole surface of the first gate oxide film
52
a
and then patterned by photolithography to thereby expose only a region
55
B, in which the medium-thickness gate oxide film
62
of the second kind of MOS transistor M
2
making up the sub-core transistor
102
is to be formed.
Next, as shown in
FIG. 6C
, residual photo-resist film
53
is used as a mask to selectively implant a fluorine (F) ion through the first gate oxide film
52
a
into the P-type silicon substrate
51
only in the region
55
B, thus forming an ion implantation layer
56
.
As described later, this fluorine ion implantation is conducted in order to obtain accelerated oxidation effects when forming by oxidation of the medium-thickness gate oxide film
62
of the second kind of MOS transistor making up the sub-core transistor
102
(
FIG. 8
) To obtain a sufficient level of the accelerated oxidation effect by use of fluorine, specifically, fluorine ions are implanted under such preset ion implantation conditions that the fluorine may have a range Rp measuring about 10 nm or less in the P-type silicon substrate
51
, in order to deposit much of the fluorine on the upper surface of the P-type silicon substrate
51
in the region
55
B.
The present applicant applied earlier a method for using argon (Ar) as an ion implantation impurity to obtain the accelerated oxidation effect in forming the medium-thickness gate oxide film (Japanese Patent Application No. Hei 12-32047, filed Feb. 9, 2000, unpublished at present). Later, however, the present applicant found that use of argon as an impurity damages the P-type silicon substrate
51
when ions are implanted, thus increasing a gate leakage current, to guard against which the present applicant found that use of fluorine in place of argon can solve such a disadvantage. Accordingly, as mentioned above, use of fluor

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