Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-16
2005-08-16
Gurley, Lynne A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S223000
Reexamination Certificate
active
06929994
ABSTRACT:
A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The method includes: (a) introducing an impurity of a second conductivity type in a specified region of a semiconductor substrate of a first conductivity type to form a first impurity layer and a second impurity layer; (b) further introducing an impurity of the second conductivity type in a region of the second impurity layer to form a third impurity layer; and (c) conducting a heat treatment to diffuse impurities of the first impurity layer and the third impurity layer to form a first well of the second conductivity type and a second well of the second conductivity type having an impurity concentration higher than the first well.
REFERENCES:
patent: 5079613 (1992-01-01), Sawada et al.
patent: 5110750 (1992-05-01), Yoshida
patent: 5238860 (1993-08-01), Sawada et al.
patent: 5260226 (1993-11-01), Sawada et al.
patent: 5514889 (1996-05-01), Cho et al.
patent: 5637524 (1997-06-01), Lee et al.
patent: 5693505 (1997-12-01), Kobayashi
patent: 5712178 (1998-01-01), Cho et al.
patent: 5895251 (1999-04-01), Kim
patent: 5917218 (1999-06-01), Choi et al.
patent: 6071775 (2000-06-01), Choi et al.
patent: 6413808 (2002-07-01), Kokubun
patent: 6451640 (2002-09-01), Ichikawa
patent: 6455402 (2002-09-01), Lee et al.
patent: 2002/0098638 (2002-07-01), Yaegashi et al.
patent: 1-268171 (1989-10-01), None
patent: 7-078881 (1995-03-01), None
patent: 8-274268 (1996-10-01), None
patent: 2000-286346 (2000-10-01), None
patent: 2000-294742 (2000-10-01), None
patent: 2001-291678 (2001-10-01), None
patent: 2001-291679 (2001-10-01), None
patent: 2001-291786 (2001-10-01), None
Gurley Lynne A.
Harness & Dickey & Pierce P.L.C.
Isaac Stanetta
LandOfFree
Method for manufacturing semiconductor device that includes... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device that includes..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device that includes... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3522801