Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-04-19
2009-10-13
Sarkar, Asok K (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21510
Reexamination Certificate
active
07601625
ABSTRACT:
A method for manufacturing a semiconductor device having a solder layer includes the steps of: grinding a mounting surface of a semiconductor chip; etching the mounting surface of the chip; forming an electrode on the mounting surface of the chip; assembling the chip, the solder layer and a base in this order; and heating the chip, the solder layer and the base to be equal to or higher than a solidus temperature of the solder layer so that the solder layer is reflowed for soldering the chip on the base.
REFERENCES:
patent: 5877079 (1999-03-01), Karasawa et al.
patent: 6596621 (2003-07-01), Copeland et al.
patent: 6911388 (2005-06-01), Kee et al.
patent: 2003/0022464 (2003-01-01), Hirano et al.
patent: 2003/0119281 (2003-06-01), Suzuki et al.
patent: 1 295 697 (1969-03-01), None
patent: 197 28 014 (1999-01-01), None
patent: A-02-144928 (1990-06-01), None
patent: A-04-312932 (1992-11-01), None
patent: A-05-243289 (1993-09-01), None
patent: A-06-196511 (1994-07-01), None
patent: A-06-333961 (1994-12-01), None
patent: A-07-176547 (1995-07-01), None
patent: A-07-263469 (1995-10-01), None
patent: A-9-277081 (1997-10-01), None
patent: A-11-74298 (1999-03-01), None
patent: A-2001-035978 (2001-02-01), None
patent: A-2002-239780 (2002-08-01), None
patent: A-2004-111607 (2004-04-01), None
patent: A-2004-119944 (2004-04-01), None
Office Action from German Patent Office issued on Aug. 14, 2006 for the corresponding German patent application No. 10 2005 018 108.2-33 (a copy and English translation thereof).
Office Action dated Mar. 13, 2009 in corresponding German patent application No. 102005018108.2 (and English translation).
Notice of Reason for Refusal issued from the Japanese Patent Office on Apr. 28, 2009 in the corresponding Japanese patent application No. 2004-124222 (with English translation).
Noritake Chikage
Okada Hideki
Sakamoto Yoshitsugu
Tanahashi Akira
Yoshida Tomomasa
DENSO CORPORATION
Posz Law Group , PLC
Sarkar Asok K
Toyota Jidosha & Kabushiki Kaisha
LandOfFree
Method for manufacturing semiconductor device having solder... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device having solder..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device having solder... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4090399