Method for manufacturing semiconductor device by using dual...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257SE21579

Reexamination Certificate

active

07598172

ABSTRACT:
A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film.

REFERENCES:
patent: 5882999 (1999-03-01), Anderson et al.
patent: 6334960 (2002-01-01), Willson et al.
patent: 6376366 (2002-04-01), Lin et al.
patent: 6548900 (2003-04-01), Kusumi
patent: 6627540 (2003-09-01), Lee
patent: 6830503 (2004-12-01), Grumbine
patent: 7071088 (2006-07-01), Watts et al.
patent: 7157366 (2007-01-01), Kim et al.
patent: 7422981 (2008-09-01), Terasaki et al.
patent: 2004/0224261 (2004-11-01), Resnick et al.
patent: 2005/0202350 (2005-09-01), Colburn et al.
patent: 2006/0213868 (2006-09-01), Siddiqui et al.
patent: 0 905 768 (1999-03-01), None
patent: 11-224880 (1999-08-01), None
patent: 11-330235 (1999-11-01), None
patent: 2004-221191 (2004-08-01), None
patent: 02/078082 (2002-10-01), None
patent: 2005/031855 (2005-04-01), None
Stephen Y. Chou, et al., “Imprint of sub-25 nm vias and trenches in polymers”, Applied Physics Letters, vol. 67, No. 21, 1995, pp. 3114-3116.
Michael D. Stewart, et al., “Direct Imprinting of Dielectric Materials for Dual Damascene Processing”, Proceedings of SPIE, vol. 5751, 2005, pp. 210-218.

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