Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
1999-11-23
2002-01-01
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S114000, C438S464000, C438S465000
Reexamination Certificate
active
06335265
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and the semiconductor device manufactured by the method, in which the semiconductor device is manufactured by using a laser-cutting a plate having a number of such semiconductor devices.
Typically, a microwave high power device such as GaAs high power FET, including a semiconductor element, includes a thinned semiconductor substrate having a small thickness of about 30 &mgr;m for an effective radiation of heat generated at a semiconductor element. Also, for further heat radiation, a radiation metal layer (PHS layer) is provided on one surface of the semiconductor substrate away from the semiconductor element.
PCT/WO98/13862 discloses a method for manufacturing a GaAs high power semiconductor device having such heat radiation metal layer, which is illustrated in
FIGS. 5A
to
5
L. According to the method, as shown in
FIG. 5A
, a first main surface of GaAs substrate
31
carrying semiconductor elements is etched to form a first separation groove
33
, in which a photoresist layer
32
provided on the first main surface is used as a mask. Then, as shown in
FIG. 5B
, the first separation groove
33
is plated with a first metal layer
34
. As shown in
FIG. 5C
, the GaAs substrate
31
then has wax
35
applied on the first main surface and is further bonded onto a supporting wafer
36
made of glass or sapphire. Also, the GaAs substrate
31
is polished at its second main surface to reduce its thickness to about 20 to 30 &mgr;m. Subsequently, as shown in
FIG. 5D
, the GaAs substrate
31
is provided at its second main surface with a photoresist layer
44
which is then patterned with an aperture opposing the first separation groove
33
. The photoresist layer
44
so patterned is used as a mask for an etching in which the second main surface of the GaAs substrate
31
is etched to the extent that the bottom surface of the first metal layer
34
in the first separation groove
33
is exposed, which results in a second separation groove
63
shown in FIG.
5
E.
Next, as shown in
FIG. 5F
, the photoresist layer
44
is removed and then a conducting layer
37
is plated on the entire second main surface of the GaAs substrate
31
. Further, as shown in
FIG. 5G
, a photoresist
45
is provided on the conducting layer
37
which is used for a mask in the subsequent plating of a second metal layer
46
made of the same metal as that of the first metal layer
34
. Afterwards, as shown in
FIG. 5H
, a photoresist layer
47
having a width smaller than that of the second separation groove
63
is formed in the second separation groove
63
. With the photoresist layer
47
as a mask, a PHS layer
38
is formed on the second main surface of the GaAs substrate
31
by the electroplating. Next, as shown in
FIG. 5I
, the GaAs substrate
31
is removed from the supporting wafer
36
. In addition, as shown in
FIG. 5J
, an expandable film
40
is attached on the PHS layer
38
. Then, the first and second metal layers,
34
and
46
, are grooved and then separated from the first separation groove
33
by exposure to laser light such as YAG laser light as illustrated by the dotted line. This results in a semiconductor device shown in FIG.
5
K. Finally, as shown in
FIG. 5L
, the semiconductor device is bonded at its bottom with a package
39
and is provided at its top with bonding wires
40
by a wirebonding technique, and then sealed in a ceramic package or a metal package not shown.
Generally, in the semiconductor device so manufactured, the topmost of the first metal layer
34
extends to a level of the first main surface of the GaAs substrate
31
. Disadvantageously, the topmost of the first metal layer
34
can extend above the first main surface of the GaAs substrate
31
because the first metal layer is formed by the plating as described above. This may cause the bonding wire
40
to make an unwanted short-circuit with the first metal layer
34
, which results in a reduction of yield rate of the device.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which no short-circuit would occur between the bonding wires and the first metal layer. Another object of the present invention is to provide a semiconductor device manufacture by the method.
Hence, the inventors of the present invention have intensively studied. As a result, the present inventors have found that the first metal layer is selectively formed in the first separation groove by an electroless plating technique using catalyst layer formed on the bottom of the first separation groove as a catalyst, so that the topmost of the first metal layer is located below that of the opening of the first separation groove, which ensures that no short circuit would occur between the bonding wire and the first metal layer, thereby accomplishing the present invention.
The present invention provides a method for manufacturing a semiconductor device, including the steps of: providing a substrate having first and second main surfaces and having a semiconductor element formed in the first main surface; forming a first groove in the first main surface of the substrate, the first groove having a bottom surface with a width and opposing side surfaces on the bottom surface; forming selectively a catalyst layer on the bottom surface of the first groove, the catalyst layer containing palladium in an upper surface thereof; forming a fist metal layer of a nickel based plating layer on the upper surface of the catalyst layer by an electroless plating technique, a top portion of the first metal layer located at a distance below a top end of the side surface of the first groove; forming a second groove in the second main surface of the substrate along the first groove, the second groove having a bottom with a smaller width than that of the bottom of the first groove and opposing side surfaces on the bottom surface, the bottom surface of the second groove being a backside surface of the catalyst layer; forming a second metal layer overlying the bottom and side surfaces of the second groove; and laser-cutting the first metal layer, the catalyst layer, and the second metal layer through the first groove.
By using such a method, the first metal layer can be formed selectively in the first separation groove so that the topmost of the first metal layer is located below that of the opening of the first separation groove, which ensures that no short circuit would occur between the bonding wire and the first metal layer.
Also, the catalyst layer containing palladium (Pd) is formed by a dry-processing technique, thereby deposition of palladium ion on outside of the first separation groove and forming nickel based plating layer on the portion where the palladium ion is deposited can be prevented.
Also, a deposit formed by reacting palladium ion and oxygen or the like can be prevented from forming on the bottom of the first separation groove.
After the step of forming the first metal layer, the method may further comprise the step of attaching a supporting member on the first main surface, and thinning the substrate through the second main surface.
Preferably, the step of forming the catalyst layer containing the steps of: forming a first photoresist layer on the first surface of the substrate, the photoresist layer having an opening opposing to the first groove; depositing a catalyst material on the bottom surface of the first groove through the first photoresist layer as a mask by evaporation or sputtering deposition; and removing the first photoresist layer together with the catalyst material on the photoresist layer, and remaining the catalyst material on the bottom surface of the first groove.
By using this step, the catalyst layer is formed selectively only on the bottom of the first separation groove.
By forming the nickel based plating layer using the palladium in the catalyst layer as a catalyst, the nickel based plating layer can be selectively formed only near t
Kosaki Katsuya
Kunii Tetsuo
Nakano Hirofumi
Chambliss Alonzo
Chaudhuri Olik
Leydig , Voit & Mayer, Ltd.
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