Method for manufacturing semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S197000, C438S207000, C438S218000, C438S220000, C438S221000, C257SE27046, C257SE27064, C257SE27108, C257SE21632

Reexamination Certificate

active

07875512

ABSTRACT:
According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.

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patent: 6737309 (2004-05-01), Matsuo
patent: 2005/0282326 (2005-12-01), Gilmer et al.
patent: 2006/0166427 (2006-07-01), Akasaka
patent: 2007/0077698 (2007-04-01), Gilmer et al.
patent: 2002-329794 (2002-11-01), None
Schram, et al., “Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only”, Symposium on VLSI Technology Digest of Technical Papers, pp. 44-45, (2008).
Kadoshima, et al., “Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS”, Symposium on VLSI Technology Digest of Technical Papers, pp. 66-67, (2007).
Sivasubramani, et al., “Dipole Moment Model Explaining nFET V1Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics”, Symposium on VLSI Technology Digest of Technical Papers, pp. 68-69, (2007).

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