Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-23
2001-11-06
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S276000, C438S279000, C438S289000, C438S299000, C438S308000, C438S526000, C438S530000
Reexamination Certificate
active
06312981
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for producing a semiconductor device, which simplifies a production process becoming complicated with the miniaturization of a complementary semiconductor device, and is capable of forming a semiconductor device which stably realizes a high-performance operation.
BACKGROUND ART
In a very large scale integrated circuit (VLSI), there has been a demand for realizing a CMOS technique capable of stably realizing high-performance transistor characteristics. However, with the miniaturization of a device and the decrease in temperature for conducting a production process, etc., point defects, i.e., vacancy and interstitial atoms (e.g., interstitial silicon), which are generated in a large number in a semiconductor substrate during an ion implantation step such as high-energy ion implantation conducted while a well and a buried layer are formed, may cause accelerating diffusion of channel impurities for controlling a threshold voltage, during a heat treatment step conducted later, which may adversely affect the re-distribution of the impurities. More specifically, undesirable problems arise, such as the fluctuations in threshold voltage, the increase in short channel effect at a time of setting a low threshold voltage, an increase in junction capacitance, a deterioration of mobility of carriers on the surface of a substrate, or a deterioration of operational performance involved therein.
In order to solve these undesirable problems, the addition of a heat treatment step for diffusing or eliminating the point defects generated by the implantation of high-energy ions, and the production process for changing a dopant used for controlling a threshold voltage into atoms which are very difficult to diffuse such as indium and antimony have been proposed.
Hereinafter, the outline of various production processes which have been proposed will be described together with problems associated therewith.
It is disclosed by J. A. Mandelman et al. in IEEE ED-L, Vol.15, No.12, December 1994 that in a buried channel-type p-MOSFET having a shallow trench separation, the dependence of a threshold voltage on a channel width varies depending upon whether or not a heat treatment step is conducted after forming a well by high-energy ion implantation. More specifically, the following is reported in the above-mentioned reference: in a buried channel-type p-MOSFET having a trench separation, the gradient of the concentration of interstitial silicon generated during high-energy ion implantation for forming a well appears in the vicinity of an oxide film on a trench side wall; as a result, the diffusion of boron forming an impurity layer for controlling a threshold voltage is suppressed more in the vicinity of the side wall of the oxide film than at a center of a channel; and the boron concentration locally increases in the vicinity of the separation side wall to cause a reverse narrow effect in which a threshold value decreases with the decrease in channel width. Considering the above, a production process for overcoming the problems associated with the above-mentioned phenomenon has been proposed.
More specifically, a trench insulation separating layer is formed on a semiconductor substrate, and ions with a first conductivity are implanted into the semiconductor substrate at a high energy (e.g., phosphorus ions are implanted at an acceleration voltage of 500 keV and a dose amount of 2.5×10
12
cm
−2
), whereby an n-well is formed. Then, in order to diffuse point defects generated by high-energy ion implantation, a heat treatment is conducted at a temperature of 800° C. for 60 minutes. Then, ions with a second conductivity are implanted at a low energy into the resultant semiconductor substrate in which the point defects are evenly distributed, whereby a channel impurity distribution for controlling a threshold voltage is formed. Thereafter, in a similar manner to that of a general process for forming a MOSFET, a gate is formed and source/drain are formed using the gate as a mask. Thus, an extraordinarily narrow channel effect is suppressed.
In IEEE ED-L, Vol.14, No.8, August 1993, pp.409-411, G. C. Shahidi et al. have proposed a production process using indium which is implanted at an acceleration energy of 190 keV as a dopant for controlling a threshold voltage. Indium is very difficult to diffuse, and forms a surface channel impurity distribution holding a retrograde shape obtained immediately after implantation, independent of the content of the step conducted before and after the ion implantation step. Therefore, a short channel effect can be suppressed even when a low threshold voltage is set.
However, the conventional methods as proposed above are not sufficiently effective for solving the above-mentioned problems described in conjunction with the point defects caused by high-energy ion implantation for forming a well.
Certainly, the first production process is effective for suppressing the local increase in boron concentration in the vicinity of the separation side wall of the buried channel. However, considering that the simplification of a production process and the decrease in production cost are demanded along with the increased demand for realizing a high density and a stable operation of a semiconductor device, the proposed modification is not preferable.
More specifically, according to the process proposed in the above reference, the heat treatment step for diffusing interstitial silicon is conducted after forming a well by the ion implantation step, and thereafter, the ion implantation step for controlling a threshold voltage is conducted. However, in order to realize such a process flow, it is required that a mask used in the implantation step for forming a well is removed to conduct a heat treatment, and thereafter, the implantation steps for respectively controlling a threshold voltage for each of a p-MOSFET and an n-MOSFET are conducted by using different, newly formed masks. Therefore, each step of mask deposition, lithography, and mask removal is actually required to be conducted four times each in relation to the implantation step for forming a well, the heat treatment step for diffusing interstitial silicon, and the implantation steps for respectively controlling a threshold voltage for each of a p-MOSFET and an n-MOSFET.
Furthermore, the above-mentioned method is effective for suppressing the local increase in boron concentration in the vicinity of the separation side wall of the buried channel. However, in view of holding a retrograde shape of a surface channel impurity distribution for controlling a threshold voltage, this method does not bring about satisfactory results.
More specifically, according to the above-mentioned method, the point defects generated by high-energy ion implantation can certainly be distributed evenly in the semiconductor substrate. However, in effect, the point defects are caused even during the ion implantation step for controlling a threshold voltage, resulting in accelerating diffusion of surface channel impurities. According to the above-mentioned method, the accelerating diffusion of such impurities cannot be suppressed.
Furthermore, when a heat treatment step is conducted on the order of minutes, impurities in a semiconductor substrate, e.g., channel impurities, largely diffuse particularly in the temperature increase step. Therefore, in the channel impurity distribution, the concentration increases on a surface and in a deep portion of the semiconductor substrate, making it difficult to maintain a retrograde shape.
In conjunction with the use of indium as a dopant, the tail portion of an impurity distribution after implantation of indium ions spreads toward a deep portion of the semiconductor substrate. Therefore, the impurity concentration in the deep portion of the semiconductor substrate after implantation of indium ions becomes higher than that when BF
2
ions are implanted at a 50% acceleration energy. As a result, the junction capacitance between the source/drain regions and the s
Akamatsu Kaori
Odanaka Shinji
Umimoto Hiroyuki
Matsushita Electric - Industrial Co., Ltd.
Pham Long
Ratner & Prestia
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