Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-21
2008-08-26
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S689000, C438S637000, C438S700000, C438S201000, C257SE21230, C257SE21304, C257SE21548, C257SE21645
Reexamination Certificate
active
07416942
ABSTRACT:
A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to reach the semiconductor substrate, filling the plurality of trenches with the silicon oxide film, removing the mask film to expose the first silicon film existing between the silicon oxide films, selectively growing a second silicon film on the first silicon film, planarizing the second silicon film using an alkaline slurry exhibiting a pH of 13 or less and containing abrasive grains and a cationic surfactant, thereby obtaining a floating gate electrode film comprising the first and second silicon films, forming an interelectrode insulating film on the entire surface, and forming a control gate electrode film on the interelectrode insulating film.
REFERENCES:
patent: 6235589 (2001-05-01), Meguro
patent: 6555427 (2003-04-01), Shimizu et al.
patent: 6649965 (2003-11-01), Takada et al.
patent: 7037784 (2006-05-01), Hong
patent: 2004/0087106 (2004-05-01), Kim
patent: 2004/0132305 (2004-07-01), Nishimoto et al.
patent: 2005/0106874 (2005-05-01), Matsui et al.
patent: 2006/0234448 (2006-10-01), Yonehama et al.
patent: 2006/0258076 (2006-11-01), Mizushima et al.
patent: 2005-109452 (2005-04-01), None
Hirasawa et al., “Methods for Manufacturing Semiconductor Devices”, U.S. Appl. No. 11/594,726, filed Nov. 9, 2006.
Hirasawa Shin'ichi
Matsui Yukiteru
Miyano Kiyotaka
Nishioka Takeshi
Shigeta Atsushi
Ahmadi Mohsen
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Geyer Scott B.
Kabushiki Kaisha Toshiba
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