Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-27
2004-03-02
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S233000, C438S241000, C438S253000, C438S303000, C438S629000
Reexamination Certificate
active
06699746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and in particular to an method for manufacturing a semiconductor device which can improve operation characteristics and reliability of the device by forming a contact plug in a cell region before forming a source/drain region in a peripheral circuit region of a semiconductor substrate to allow a high temperature process.
2. Description of the Background Art
In general, a PN junction is formed by ion-implanting an N type impurity or P type impurity into a P type semiconductor substrate or N type semiconductor substrate, and activating the resultant substrate via a thermal process to form a diffusion region.
Therefore, a shallow junction is required to prevent a short channel effect due to lateral diffusion from the diffusion region in a semiconductor device having a reduced channel width.
A conventional method for manufacturing a semiconductor device will now be explained.
An device isolating insulation film defining an active region is formed in a cell region and a peripheral circuit region of a semiconductor substrate.
A stacked structure of a gate insulating film, a conductive layer for gate electrode and a mask insulating film is formed on the entire surface of the resultant structure.
The stacked structure is then etched using a gate electrode mask as an etching mask, thereby forming a stacked structure of a gate insulating film pattern, a gate electrode and a mask insulating film pattern.
Thereafter, a first insulating film is formed on the entire surface of the resultant structure. Here, the first insulating film is composed of a nitride film.
A low concentration impurity is ion-implanted into the entire surface of the resultant structure, thereby forming a lightly doped drain (LDD) region on the semiconductor substrate at both sides of the gate electrode.
A second insulating film is formed on the entire surface of the resultant structure. Here, the second insulating film is composed of a nitride film to form the LDD structure.
An insulating film spacer is formed on the sidewalls of the stacked structure of the gate insulating film pattern, the gate electrode and the mask insulating film pattern by etching the second insulating film and the first insulating film in the peripheral circuit region of the semiconductor substrate.
Then, a source/drain region is formed by ion-implanting a high concentration impurity into the semiconductor substrate at both sides of the insulating film spacer. In the case of a high speed logic process, a silicide film is formed in the source/drain region.
A first interlayer insulating film is then formed on the entire surface of the resultant structure.
Thereafter, a contact hole is formed by etching the first interlayer insulating film, the second insulating film and the first insulating film using a contact mask which expose a predetermined region for bit line contact and storage electrode contact in the cell region of the semiconductor substrate as an etching mask, and an insulating film spacer is formed on the sidewalls of the stacked structure of the gate insulating film pattern, the gate electrode and the mask insulating film pattern. Here, the insulating film spacer is composed of the first insulating film.
A conductive layer composed of a polysilicon layer is formed on the entire surface of the resultant structure.
A contact plug is formed by removing the conductive layer and the first interlayer insulating film via a chemical mechanical polishing (CMP) process.
A second interlayer insulating film is formed on the entire surface of the resultant structure.
Thereafter, the second interlayer insulating film is etched to form a bit line contact hole using a bit line contact mask as an etching mask.
As described above, in the conventional method for manufacturing the semiconductor device the source/drain region in the peripheral circuit region of the semiconductor substrate is formed before the contact plug which connected to the predetermined region for the bit line contact and storage electrode contact in the cell region is formed. However, a subsequent process must be performed below 800° C. to maintain a low contact resistance in the source/drain region. This deteriorates a filling characteristic of the interlayer insulating film and restricts a deposition temperature of the conductive layer for forming the contact plug. In addition, since the entire second insulating film in the cell region must be removed, the first insulating film surrounding the gate electrode is ununiformly damaged. Furthermore, the property of the logic process employing a technique of forming the silicide film after forming the source/drain region is deteriorated due to a thermal process for forming the contact plug, and thus the DRAM technique and the logic high speed process cannot be used together.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent characteristics of the device from being deteriorated resulted from a thermal process by forming a contact plug in a predetermined region for a bit line contact and storage electrode contact in a cell region of a semiconductor substrate, and then forming a source/drain region in a peripheral circuit region.
In order to achieve the above-described object of the invention, there is provided a method for manufacturing a semiconductor device including the steps of: forming a first insulating film on a semiconductor substrate having a cell region and a peripheral circuit region, each region having a gate electrode formed thereon; forming an LDD region on the semiconductor substrate at both sides of the gate electrode; forming a first interlayer insulating film on the entire surface of the resultant structure; forming a first insulating film spacer on the sidewalls of the gate electrode in the cell region by etching the first interlayer insulating film land the first insulating film in the cell region using a contact mask exposing a bit line and storage electrode contact region as an etching mask; forming a conductive layer electrically connected to the exposed bit line and storage electrode contact region; removing the first interlayer insulating film in the peripheral circuit region; forming a second insulating film on the entire surface of the resultant structure; forming a second insulating film spacer on the sidewalls of the gate electrode in the peripheral circuit region by etching the second insulating film and the first insulating film; forming a source/drain region by ion-implanting a high concentration impurity into the semiconductor substrate at both sides of the second insulating film spacer; forming a second interlayer insulating film on the entire surface of the resultant structure; and forming a contact plug by planarizing the second interlayer insulating film, the first interlayer insulating film and the conductive layer.
The first insulating film comprises a nitride film having a thickness of 20 to 400 Å.
The first interlayer insulating film is selected from the group consisting of borophospho silicate glass (BPSG) film, tetraethyl ortho silicate (TEOS) film, high density plasma (HDP) oxide film, and combinations thereof.
The conductive layer comprises a polysilicon layer doped with an n type impurity.
The conductive layer is an epitaxially grown silicon film.
The step for forming the source/drain region further includes a step for forming a silicide film on the source/drain region.
The second insulating film comprises a nitride film having a thickness of 20 to 400 Å.
The second interlayer insulating film is selected from the group consisting of high density plasma (HDP) oxide film, tetraethyl ortho silicate (TEOS) film, advanced planarization layer (APL) film, undoped silicate glass (USG) film, and combinations thereof.
REFERENCES:
patent: 5895239 (1999-04-01), Jeng et al.
patent: 6344389 (2002-02-01), Bronner et al.
patent: 6372571 (2002-04-01), Ki
Chung Su Ock
Lee Sang Don
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Quach T. N.
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