Method for manufacturing semiconductor device

Details Method for manufacturing semiconductor device Method for manufacturing semiconductor device

2000-07-17

2004-04-20

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S712000, C438S723000, C438S724000

Reexamination Certificate

active

06723647

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device in which the processing conditions of a non-cell region is improved to decrease a defect generating ratio at a cell array region, which ultimately increases the manufacturing yield.
Generally, in the manufacturing process of a semiconductor device, a number of steps are required to process a non-cell region to obtain a necessary cell array region that is needed for the highly integrated circuit chips. An alignment mark is an example of the non-cell region. The alignment mark is needed for a correct exposure of light onto a corresponding position of a circuit during numerous implementations of a photolithographic method that are required in the manufacture of the semiconductor device. The alignment mark is separately formed on a region such as a scribe line or an edge device that will be discarded after final production.
The role of the alignment mark will now be described in more detail. Conventionally, a semiconductor device is manufactured by repeating a process of depositing various materials and then patterning the same a number of times. A desired shape of a material layers is obtained by using the structure of a preceding layer. In other words, the preceding material layer and a photomask must be correctly aligned for the light exposure to obtain an accurate photoresist pattern during a number of accompanying photolithography processes.
However, as the deposition of various materials proceeds, the crookedness of the material layer gradually disappears and the circuit pattern on the cell array region becomes more complicated. Therefore, the correct alignment of the photomask for the subsequent layers over the underlying material layer becomes difficult. To solve this problem, a number of alignment marks are formed in a certain region, for example, on a scribe line, with respect to the material layers obtained at each step of the manufacturing process. The alignment marks are not integral parts of the device, but they are formed as a circuit of the non-cell region to assist the manufacturing process. Methods for manufacturing such alignment marks are disclosed by U.S. Pat. Nos. 5,369,050 (issued to Kawai), 5,663,099 (issued to Okave et al.) and 5,786,267 (issued to Karguchi et al.).
A lot ID illustrates another example of a non-cell region. The lot ID is formed in an appropriate region on a wafer by labeling a number or a symbol by means of a laser after inspecting the wafer and prior to processing the wafer for device manufacturing. The lot ID generally includes lot designating symbols and wafer designating symbols for differentiating each wafer. One lot includes one bundle of wafers to be processed by the manufacturing process. The lot ID, which is formed for the purpose of designation, is also used as an alignment mark as needed. However, the lot ID commonly becomes covered by various materials during the progression of the device manufacturing process.
Edge devices not having proper sizes of unit devices and which remain at the edge portions of the wafer, offer a third example of the non-cell region. The formation of the edge devices are due to the shape of the wafers. In other words, because the shape of the wafers is not square but is circular, a number of edge devices are formed along the edge portion of the wafers. Semiconductor devices are not formed on the edge devices but various layers of materials are formed on the edge region during the manufacturing process. Generally, alignment marks are formed on these edge devices.
In the non-cell region described above, the applied material formed on the cell array region during each step of the manufacturing process is also simultaneously formed. However, unlike in the cell array region, independent conductive patterns which are not earthen to the underlying silicone substrate, i.e., which are not connected to ground, are formed at the non-cell regions. As a result, the independent conductive patterns may be exposed during a subsequent dry etching using ion-assisted plasma. At this time, the generated ions and plasma may be electrically charged, and when a critical point has been reached by the movement of the etching plasma, the exposed independent patterns may instantaneously discharge, causing an arcing phenomenon. Once the arcing is generated, the region where the arcing has originated may melt or materials around the arcing generated portion may randomly tear off, potentially causing a 0% yield for the wafer. The arcing may also damage the existing alignment marks, resulting in a misalignment of the photomask with the cell array region during the subsequent photolithography process, also resulting in a decreased yield.
The arcing phenomenon will be explained in more detail with reference to the alignment mark.
FIG. 1
is a cross-sectional view showing the structure of an alignment mark AM manufactured by a conventional method. A gate electrode material layer
12
including a polysilicone layer
12
a
and tungsten silicide (WSi) layer
12
b
, is formed on a silicone substrate
10
. A first oxide layer
13
and a first insulation layer
14
are formed on the gate electrode material layer
12
. The first oxide layer
13
is a high temperature thermal oxide layer, and the first insulation layer
14
is preferably an undoped silicate glass (USG) layer. A bit line material layer
15
is formed on the first insulation layer
14
. The bit line material layer
15
includes a polysilicone layer
15
a
and a tungsten silicide layer
15
b
. A second insulation layer
16
, i.e. a borophosphosilicate glass (BPSG) insulation layer, and a second oxide layer
17
, which is another high temperature thermal oxide layer, are subsequently formed on the bit line material layer.
During the formation of the alignment mark (AM) by an integration of the various materials mentioned above, a cell array region of the device is formed as follows. A gate electrode is formed on the substrate and is then electrically insulated. Then, a bit line, which is connected to an impurity doped region, i.e. a source/drain region, is formed and is electrically insulated by depositing an insulating material on the substrate. Thereafter, a portion of the insulating material is removed to form a contact hole that exposes the impurity doped region, i.e. the source/drain region on the substrate. A storage node is then formed on the insulating material so that the source/drain region and the storage node are connected through the contact hole.
The structure illustrated in
FIG. 1
is obtained at the step of forming a photoresist pattern
18
on the second oxide layer
17
. The photoresist is formed by depositing a photoresist and then opening a portion to be etched for the formation of the contact hole. After this step, the portion opened by the photoresist pattern
18
is etched and removed down to the upper portion of the substrate to form the contact hole. At the same time, an etching is simultaneously implemented at the alignment mark region for the formation of an alignment mark that will be used for the subsequent photolithographic process. However, unlike in the cell array region, the gate electrode material layer
12
and the bit line material layer
15
are not earthen to the substrate, i.e., they are not connected to ground, and are independently formed as conductive patterns at the non-cell region. Accordingly, when an ion-assisted plasma dry etching is implemented and these independent conductive patterns are exposed to the plasma, arcing might be generated.
FIG. 2
is a cross-sectional view for showing the structure surrounding the alignment mark of
FIG. 1
when an arcing is generated by a reactive ion etching process. The reference numeral
11
designates an etched portion around the alignment mark. The portion where the arcing is generated is melted away as shown by an arcing generating portion
19
. Otherwise, the arcing generated port

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