Method for manufacturing semiconductor device

Details Method for manufacturing semiconductor device Method for manufacturing semiconductor device

1999-02-18

2002-06-04

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S398000

Reexamination Certificate

active

06399439

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device of a stacked capacitor type memory cell having on a substrate a cylindrical member having a bottom and no top made of polysilicon, and more in particular to the method for manufacturing the semiconductor device having the stacked capacitor type memory cell equipped with a capacitor having a. large electrostatic capacity per occupied unit area.
(b) Description of the Related Art
Recently, in a semiconductor memory device such as DRAM (Dynamic Random Access Memory), a demand of decreasing a required area of each memory cell for attaining high integration is highly desired. In order to respond to this demand, it is important to form a capacitor having a large electrostatic capacity per occupied unit area in each of the memory cells.
The increase of the electrostatic capacity, of either of an upper electrode or a lower electrode of each of the capacitors, for example of the lower electrode, is attempted by employing a cylindrical electrode as the lower electrode. Moreover, the surface area of the electrode is increased by forming a layer of hemispherical silicon nuclei (HSG-Si: Hemi-Spherical Grained Si) on the cylindrical electrode surface to make the electrode surface uneven so as to further increase the electrostatic capacity.
First, a method for forming a conventional cylindrical lower electrode having the hemispherical silicon grains applied for making a stacked capacitor type memory cell will be described with reference to
FIGS. 1
to
6
.
FIGS. 1
to
6
are sectional views suquentially showing the respective layered structures including a substrate of each of the steps for conducting the above method.
(1) In a conventional method, an element separation film
14
is formed on a silicon substrate
12
, and a gate oxide film is formed in a region after the element separation as shown in FIG.
1
. Then, the formation of gate electrodes
16
A,
16
B followed by that of source/drain diffusion regions
18
makes two adjacent n-MOSFETs.
Then, an interlayer insulation film
20
made of -a BPSG film and a first silicon oxide film
22
are successively formed on the whole substrate
12
surface.
Through holes for exposing the source regions
18
are perforated through the first silicon oxide film
22
and the interlayer insulation film
20
, and the through holes are filled with phosphorus (P) doped amorphous silicon film (hereinafter referred to as “P-doped Si film”) to make capacitance contact plugs
24
which are electrically connected with the source regions
18
.
A silicon nitride film
26
, a spacer layer
28
made of a BPSG film and a second silicon oxide film
30
are successively layered on the whole substrate surface. The patterning by means of photolithography is conducted to etch the second silicon oxide film
30
, the spacer layer
28
and the silicon nitride film
26
to form openings (concaves)
32
for making lower electrodes. The layered structure shown in
FIG. 1
is obtained.
(2) Then, a P-doped Si film between 1000 and 1500 Å is grown along the whole open walls of the openings
32
under the below conditions for growing an intermediate. layer
34
for forming the cylindrical lower electrode (hereinafter referred to as “cylindrical member
34
”) as shown in FIG.
2
. In
FIG. 2
, a numeral
36
designates an outer part of the P-doped Si film, or a phosphorous doped amorphous silicon originally grown layer (hereinafter referred to as “originally grown layer”) in contact with the opening wall of the openings
32
.
Conditions for Growing P-Doped Si Film
Reaction Gas: SiH
4
+PH
3
Temperature for Growing: 525 to 535° C.
Pressure: 1.5 to 2.0 torr.
(3) Silica glass is then spin-coated on the whole substrate surface to form a silica film (SOG) which is etched back to obtain a layered structure having a silica layer
38
on the cylindrical member
34
as shown in FIG.
3
. The silica layer
38
is employed for protecting the bottom part
35
of the cylindrical member
34
from being etched when the P-doped Si film is etched. A resist film or the like can be used in place of the silica film
38
as long as it functions as a protection film.
(4) The silica film
38
is then etched employing the second silicon. oxide film
30
as an etching stopper as shown in FIG.
4
.
(5) The second silicon oxide film
30
and the spacer layer
28
are then etched employing the silicon nitride film
26
as an etching stopper to expose the outer and inner wall surfaces of the cylindrical member
34
made of the phosphorous doped amorphous silicon (lower electrode intermediate) as shown in FIG.
5
.
(6) The silicon nitride film
26
employed as the etching stopper is then removed by the etching without etching the cylindrical member
34
to expose the first silicon oxide film
22
as shown in FIG.
6
.
(7) After the above procedures are completed, the cylindrical member
34
is subjected to a treatment for making hemispherical silicon grains employing a reaction furnace preferably in a batchwise operation as follows. The above treatment of the cylindrical member
34
may be performed successively in a sheetwise operation.
(i) A wafer having the above layered structure is sent to the reaction furnace, and a temperature is elevated under high vacuum to 560° C. and maintained for 30 minutes. This step is called a temperature stabilization step.
(ii) An SiH
4
gas is introduced into the reaction furnace at a rate of 75 sccm while maintaining the temperature of 560° C. and the wafer is irradiated with the above gas for 20 minutes. Si crystal nuclei are thereby formed on the P-doped Si film
34
. This step is called an SiH
4
irradiation step.
(iii) The wafer is then subjected to an annealing treatment under high vacuum maintaining the temperature of 560° C. The Si crystal nuclei are thereby grown to become the hemispherical grains by means of integrating the silicon atoms in the P-doped Si film on the Si crystal nuclei formed on the P-doped Si film. This step is called an annealing step. During the treatment of making the hemispherical grains, the P-doped Si film is converted into a phosphorous doped polysilicon film by means of the annealing treatment.
After the above procedures, the surface of the cylindrical member
34
has been formed by the hemispherical grains.
In the above treatment, however, among the hemispherical silicon grains formed on the surface of the cylindrical member
34
, those on the outer wall surface have non-hemispherical grain surfaces
42
and uneven shapes though those on the inner wall surface have hemispherical grain surfaces
40
of a uniform and preferable grain radius as shown in FIG.
7
. Moreover, the grain size of the former becomes excessively large so that the respective grains are in contact with one another not to increase the surface area of the cylindrical member to an expected value.
With the miniaturization of memory cells, a cell pitch between the memory cells becomes extremely small, and an interval between two adjacent cylindrical lower electrodes becomes short accordingly. For example, in the direction of a shorter side of the lower electrode, a width of the cylindrical member is 0.25 to 0.40 micronmeter while an interval between the electrodes is 0.15 to 0.18 micronmeter. On the other hand, in direction of a longer side of the lower electrode, a width of the cylindrical member is 0.70 to 0.78 micronmeter while an interval between the electrodes is 0.20 to 0.23 micronmeter. These intervals are extremely short. When, therefore, the grain size
42
becomes excessively large, the outer walls of the adjacent cylindrical members are likely to be in contact with each other via the grains to produce a short-circuit between the adjacent electrodes.
These defects may reduce the effectiveness of producing the hemispherical grains on the surface of the cylindrical member, and the realization of the memory cell having a large electrostatic capacity is difficult, and the memory cell having a high electrical reliabil

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