Method for manufacturing self-aligned split-gate flash memory ce

Details Method for manufacturing self-aligned split-gate flash memory ce Method for manufacturing self-aligned split-gate flash memory ce

1997-05-21

1999-01-05

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, H01L 218247

Patent

active

058562230

ABSTRACT:
A method for manufacturing self-aligned split-gate flash memory cells wherein the split-gate structure is formed by a self-aligned approach, so that the length of a channel can be precisely controlled. Furthermore, sources and drains are formed separately by executing different implantations, so that the dopant parameters of the sources and drains can be changed, based on desired and possibly different characteristics.

REFERENCES:
patent: 5364806 (1994-11-01), Ma et al.
patent: 5482879 (1996-01-01), Hong
patent: 5482881 (1996-01-01), Chen et al.
patent: 5607871 (1997-03-01), Han
Naruke, et al., "A New Flash-Erase Eeprom Cell with a Sidewall Select-Gate on Its Source Side," IEDM Tech. Dig., pp. 603-606 (1989).
Ma., et al., "A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications," Symposium of VLSI Tech. Digest of Tech. Papers, pp. 49-50 (1994).

Affiliated with

Also associated with

Rating

Method for manufacturing self-aligned split-gate flash memory ce does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing self-aligned split-gate flash memory ce, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing self-aligned split-gate flash memory ce will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-861869