Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-19
2001-04-03
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S655000
Reexamination Certificate
active
06211027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a P-type metal-oxide-semiconductor (PMOS) transistor.
2. Description of the Related Art
Advances in the techniques of miniaturizing and integrating devices together have made the fabrication of deep submicron circuits possible. Due to a reduction of line width, contact area and junction depth, contact resistance is increased correspondingly. With an increase in contact resistance, signal transmission rate is reduced. To decrease contact resistance and increase signal transmission rate, an additional self-aligned silicide layer is usually formed on top of each contact terminal.
In general, the self-aligned silicide layer is formed only after the gate terminal, the spacers and the source/drain terminals of a MOS transistor are all formed. The self-aligned silicide process includes sputtering titanium over the MOS transistor. A first rapid thermal process (RTP) is next carried out at a temperature between about 620 and 680° C. in a nitrogen-filled atmosphere. Titanium reacts with silicon to form a C-49 phase titanium silicide layer over the gate terminal and the source/drain terminals. Titanium nitride and unreacted titanium is subsequently removed. A second rapid thermal process (RTP) is carried out at a temperature between about 800 and 900° C. to the C-49 phase titanium silicide into C-54 phase titanium silicide. Since no photolithographic processing step is involved, the self-aligned silicide process has become a highly attractive method for making metal contacts.
In the manufacturing of MOS transistor with a feature line width smaller than 0.18&mgr;m, the second rapid thermal process is usually carried out at a temperature below 850° C. for a duration of about 20 seconds. However, when the titanium silicide layer has a narrow line width, the so-called narrow line width effect becomes dominant. In other words, due to the presence of a smaller number of nucleation sites, phase transition of titanium silicide layer from the high resistance C-49 phase to a low resistance C-54 phase is harder. To ease the phase transition, the second RTP must be carried out at a higher temperature. Alternatively, the titanium silicide is heated to a temperature of about 850° C. and maintained there for a period of about 10 seconds. The temperature of the titanium silicide is suddenly raised to about 975° C. for a brief moment followed by a rapid cooling. Rapid cooling prevents the agglomeration of titanium silicide at high temperature, which might damage the surface structure at the gate and the source/drain terminals.
FIG. 1
is a graph plotting sheet resistance of titanium silicide versus NMOS polysilicon critical dimension for a second rapid thermal process of heating to 850° C. (plotted with squares) and a second rapid thermal process of heating to 850° C. with a spike heating up to 975° C. (plotted with circles). The instantaneous heating and rapid cooling of the titanium silicide layer is quite effective in reducing the resistance of titanium silicide layer. In particular, when critical dimension of feature line width is reduced to 0.14 &mgr;m, sheet resistance Rs at the source/drain terminals can still be maintained at around 4 &OHgr;/□ (ohms/square unit). Consequently, a relatively high process window is provided. Compared with heating to a temperature of about 850° C. for a duration of 20 seconds, sheet resistance at the source/drain terminal reaches 10 &OHgr;/□ when critical dimension of feature line wide is reduced to 0.14 &mgr;m.
However, a sharp increase in temperature followed by rapid cooling for transforming the phase of the titanium silicide layer causes some problems for the P-type MOS transistors. This is because boron ions are often used as dopants in the source/drain terminals of a PMOS transistor. Since boron ions have a relatively small ionic radius, the ions can easily diffuse into the silicon oxide layer on the surface of the silicon substrate when the temperature is raised to about 975° C. in the second RTP. An outward diffusion of boron ions lowers the dopant concentration in the source/drain terminals. Consequently, there is a lowering of drain current (I
D
).
FIG. 2
is a graph plotting residual drain current I
off
versus ion concentration for a PMOS transistor having a silicide layer formed by a conventional self-aligned silicide process (plotted with squares) and a PMOS transistor having a silicide layer formed by a self-aligned silicide process with a spike heating up to 975° C. (plotted with circles). For identical residual current I
off
when both PMOS transistors are off, drain current I
on
of a PMOS transistor is attenuated by about 8% if spike temperature heating has been used during the silicide process.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a PMOS transistor. To form the PMOS transistor, a P-type substrate is provided. A gate terminal is formed over the substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal suicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are then removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is formed in the substrate interior under the source/drain extension region.
In this invention, the source/drain extension region is formed after the metal silicide layer is formed over the gate terminal and the source/drain terminals. There are several advantages to this processing arrangement. First, processing parameters in the original self-aligned silicide process can be retained so that a PMOS transistor with better electrical properties is obtained. Second, concentration of dopants within the source/drain terminals can be maintained so that attenuation of drain current due to heat processing can be prevented. Third, the self-aligned silicide layer serves directly as an ion mask for forming the source/drain extension region and the anti-punchthrough region of the PMOS transistor. Hence, the increase in junction capacitance due to the implantation of ions into the lower edge of the source/drain terminals can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5702986 (1997-12-01), Mathews et al.
patent: 5866460 (1999-02-01), Akram et al.
patent: 5899719 (1999-05-01), Hong
patent: 5981383 (1999-11-01), Lur et al.
patent: 6015752 (2000-01-01), Xiang et al.
Hsue C. C.
Lin Tony
Charles C. H. Wu & Associates
Smith Brad
United Microelectronics Corp.
Wu Charles C. H.
Zarabian Amir
LandOfFree
Method for manufacturing PMOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing PMOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing PMOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2498662